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Thank you all very much!!

I tried to do the same with 2 different PCs:
https://i.imgur.com/ZP9e7cU.png

I clicked on 'apply' then cleared output files and built all again.
But nothing has been changed in the *.lst file.
...

Ttelmah - thank you very much!

Here is a tip. Post your .LST file segment in Symbolic mode.
It's easier to understand and interpret code when in that mode.

Here are instructions from Ttelma ...

I am grateful for your test.

I just compiled a dummy project for your chip, with the clock selected
as you are doing, and the changes made to the processor file. It shows
it setting PLLFBD to 0x3 ...

Thank you for your guide. I did it and the difference is only in line 268:

.................... #use delay(oscillator=25M, clock=100M)
*
00262: CP0 W0
00264: BTSC.B 42.1
00266: BRA ...

Thanks for the very informative explanation.

Could you also help with CPU clock issue?
Can I see the disassembly of #use delay() to detect the prescalers values?

Thanks for your response and ti ...

Ttelmah
Thanks, I know the meaning, so I can use with this even if not appear in the list of supported fusses from <24ep512GP806.h>:

#nolist
//////// Program memory: 175104x24 Data RAM: 53 ...

Thanks for your response and time.

1.
The question about the invalid CPU clock is not only above MAX, it can be also lower than MAX but doesn't meet the limits and constraints in the PLL diagram ...

Hi all,
I am using pic24ep512gp806, CCS PCD C Compiler, Version 5.093.

1.
What is happening in case I set #use delay() with invalid value CPU clock (according to datasheet)?

#use delay(oscill ...