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asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
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 Posted: Mon Nov 28, 2011 11:18 am |
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i have a code library that does the 28 bit math for AD9833 with fractional HZ resolution yet does NOT need floating point to do any lifting.
( how can that be you ask ? :;-):
The whole driver is very few lines of code using ONLY integer math -and is very very fast - even on 16F chips. my advantage is that ALL master clock frequencies are NOT created equal 
however to be able to help you i need to know several things:
1- what chip are you programming for?
2- is your master clock frequency SET in stone ??
3- what is the smallest output frequency interval that you REALLY need?
HINT: the secret is to use an EXACT power of 2 as the oscillator reference.
I use 16,777,216, 8.388608 and 4.194304 mhz typically .
BTW: if you are really trying to head for 1 GHZ land then a PLL generated 1.07374 GHZ Fref might be doable for you. |
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PICman
Joined: 02 Nov 2007
Posts: 26
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| Posted: Sat Dec 03, 2011 9:23 am |
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@lifespeed
I also work on source code to eventually address a 48-bit DDS chip (AD9854/56 from AD). I presently use the 32-bit AD9850 for now... And althrough double precision float would be the easy-way to do things, i realise that 64-bit INT is way easier to implement...
Give us some news on your project...
You also mentioned that you required exponentiation for your project... I guess that the purpose of exponentiation is to do a log sweep. I suggest you to use single precision float to calculate the log sweep itself and then cast to INT-64 to address the DDS. And for precise frequency control purposes, well, do it all in INT-64.
And for those who would like to experiment with DDS to build a fine signal generator, there are plenty of AD9850 (0-40 MHz output / 125MHz clock / 10 bit resolution / 32-bit freq word) IC's and modules available on eBay for cheap !
_________________
The ideal electronic world: A place where the words VERSION and REVISION do NOT exist ! |
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asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
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| Posted: Sun Dec 04, 2011 11:35 am |
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| Quote: |
double precision float would be the easy-way to do
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actually simple shifts will suffice for two 16 bit integers - a "hi part"
and a "lo part" of a 32 bit divisor
ad9833 divisors fall in to line perfectly when you use that power of two oscillator frequency i mentioned, especially when you take advantage of
the partial register update method that chip allows.
with a core freq of 8.388608 mhz
| Code: |
void DDSdrv( unsigned int16 xmitword ){
DNO_LS=0; // lower BAR-cs
SPI_write(make8(xmitword,1)); // send the hi byte first
SPI_write(make8(xmitword,0)); // then the LOW byte
DNO_LS=1; //
}
// infreq is an unsigned int32 of desired frequency in HZ
// hipart,lopart are unsigned int16
// assume 4194304 freq ref
// hipart= (infreq >> 8);
// lopart= ((infreq<<6) & 16383 );
// below is 8388608
hipart= (infreq >> 9);
lopart= ((infreq<<5)&16383 ); //
DDSdrv( (0x4000+lopart ));
DDSdrv( (0x4000+hipart ));
// keep in mind you MUST properly intialize the ADS9833
// to use this very fast frequency update method
// below is PART of what you have to do to initialize properly
// but not every detail is shown
DNOdrv(0x2100); // send RESET SIN word case 0 and 1 for now
DNOdrv(0xC000); // send PHASE CTL word to mid scale
DNOdrv(0x2000); // send RESET SIN word case 0 and 1 for now
// the limits of this method are set by the choice of master clock
// YET NOTE: you dont absolutely NEED an exact power of two
// since you can manipulate infreq in various INTEGER divisible
// FRACTIONAL ways that do not need floating point either.
// EG: with a ref freq of 10.485 mhz you would scale the input by 3/4
// as in: corrected_infreq = (infreq*3)/4;
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