I2C Master Wait

[Guest]

Hi,
I had a question regarding the I2C Master wait possibility!! My understanding of the I2C interrupt is that, when a master writes the slave address, the slave matches the address, and sends an ACK, and then sets the #INT_SSP.
This directs the slave operation to : void ssp_interupt ().
I was wanting to know, if I do not want to use an interrupt. And if I have a regular infinite loop in the slave. Is it possible for the master to wait till I reach the part in the slave code that checks if the master is asking for data. And then replies with data.
And if its possible could I basically start the I2C code in my main slave code with:

state = i2c_isr_state();

if(state < 0x80) // MASTER SENDING DATA
��. And so on.

Basically my slave code will be an infinite loop. It will perform the necessary calculations, and will check for the i2c_isr_state status once an iteration. I presume the master will receive an ACK as soon as it sends the address of the slave.Since, this happens through the hardware. But then, will the master wait for the slave to respond. Since the slave could be somewhere in the infinite loop, and could take a while to reach the point where it checks for I2C request.

[Ttelmah]

Look carefully at the 'slave mode' description in the chip data sheet.
When the master requests a 'read' from a slave device, and the address is matched, the ACK is generated, and the clock line is held low by the slave, until it's code clears this bit. This is called 'clock stretching', and can be enabled for all transactions. For the read transaction, it is always enabled (can't be turned off). The master has to wait till the clock line is released, before it can start the next transaction. The reason it is compulsory for the read transaction, is that for this one, the slave needs to load the returned data before the master can start clocking. For other transactions, the single character of buffering represented by the input shift register, is normally enough for this not to be needed.
So the hardware contains both a buffer (for incoming data), and a mechanism to allow the slave to make the master 'wait' while it gets ready.
Now depending on youir likely loop time, the hardware buffer may well be all that is needed (remember, even at 400KHz, it takes 20uSec to transfer a byte, and provided your loop is fast, this may well be enough time. However if it is likely not to be enough, then you need to enable the clock stretching for other transactions. The default settings in CCS, enable this.

Best Wishes