Using chip select line for bidirectional signaling on SPI

[libor]

The scenario:
I have a 18F series PIC (master) some additional SPI devices (RTC, RAM, flash) and an another PIC (slave). Both PICs have hardware SPI, each chip has its own dedicated Chip Select (SPI enable) line coming from the master PIC, that pulls it low when it wants to communicate with that slave.
The slave PIC has this chip select line connectied on its SS pin.

The communcation will be mostly done in polling mode, it is master that initiates the talk. However I would like the slave PIC to notify the master PIC that it has some data to transfer. This way I would eliminate the unnecessary polling if the slave has nothing to say.

I planned to use a separate pin on the master for the chip select and another one (INT0-INT2) to get an interrupt when the slave has something to say on the SPI bus, but I have run out of pins on the master.


The question is, can I use the Chip Select line between the two PICs for a bidirectional communication in this way: (it is the connection between master PIC's B0 INT0 pin and the slave PIC's SS pin)

1. most of the time it would be set to INPUT on both PICs, pulled HIGH with an external resistor (ie. chip select not active on the slave with the SPI in slave (listening) state, and no interrupt request on the master)

2. If the master wants to talk to the slave PIC, it switches the B0 (INT0) to OUTPUT and sets it LOW, and the SPI trasfer goes as normally.

3. If the slave has some data it turns off the SPI slave mode for a moment, drives its SS pin for some msec to LOW initiating an interrupt in the master (the master would have an interrupt set to INT0 H->L edge), and then immedatelly swithes back to SPI slave mode waiting for the master to ask for the data on the SPI in the normal way using the SS pin normally, as a Chip Select line.

I am aware that this method can cause some bus arbitration conflict in the unlikely case the PICs want to speak to each other at the very same time, but both PICs would only bring this line to a LOW state, so no overcurrent may occur, I would also use a series resistor to limit the current for added security. The software would repeat the undelivered message in such cases (with a different retry delay in the slave and in the master).

What do you think guys? Can I share the usage of the Chip Slect SS line of the slave PIC to notify the master PIC thru it making it bidirectional ?

[RLScott]

You might be able to do this, but it will be very tricky. The only way you can drive the SS pin from the slave is to setup the slave with SS disabled, so it can be used as a GPIO. But then when you want to actually receive a transaction from the master, you need to re-configure the SPI on the slave to enable SS. There are lots of opportunities for bad things happening simultaneously. It might help if the slave checks the SS is high before beginning a "signaling" to the master, although even that will not totally eliminate collisions, as you pointed out. But I suppose if you are out of pins, you do what you need to do.
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Robert Scott
Real-Time Specialties
Embedded Systems Consulting