50Hz Referenc sine signal synchronized with voltage waveform

[pad]

Hi all,
I am planning to produce a ref. 1Volt sine signal syncronize with voltage Zero Crossing.
I am using PIC16F72 & MCP4821 DAC, CCS 4.020.
I am able to generate sine wave using LUT with 120 samples synch with ZCD.In between delay of 167us approx in each sample. If frequency change is less than 167 us I have to neglect last sample(120th) which disturb the shape of waveform and its accounts more THD in output waveform.
Is there any other method to do this task? I am also working on PLL 4046 circuit,but it will be a complete analog system and THD 2.5% for 50Hz . I need Some thing mix of analog & digital with good accuracy & low THD. Looking for some IDEAS from you guys.
- Following you guys from 3 - 4 years.Good forum.Nice Peoples.Good Help.

Thanks,
PAD

[asmboy]

what is the application?

what range of frequency?

how important is the zero crossing?

how much jitter allowed in zero cross detection?


how low a sine THD is neccessary and why ??

[Mike Walne]

25 years ago I joined a company which was using the following to generate a clean 50Hz sync'd sine wave.

Zero crossing detect used to create 50Hz reference.
4046 oscillator fed to an 8 stage binary divider.
Divide by 256 O/P was compared to 50Hz reference to control the 4046's PLL oscillator.
Each stage of binary divider was fed to address input of a ROM.
ROM data outputs fed to D2A converter.

Job done. No programming need apart from data for ROM.

If you use a 256 step generator that's enough information to calculate expected THD etc.

Mike

[pad]

thanks asmboy & Mike Walne,

what is the application? - generating 1V ref. voltage synchronous to input utility voltage which has changing amplitude & frequency. But Generated Ref. signal should have constant Amplitude and matching frequency.
Project is Industrial Front end for load

What range of frequency? 50Hz/60Hz

How important is the zero crossing? - Most important.Output is stabilized voltage.

How much jitter allowed in zero cross detection? - planning for 1%

How low a sine THD is neccessary and why ?? - less than 1%. Product should confirm 2% accuracy. So generation has to be less or equal to 1%

To Mike Walne -
I am following same logic now as you have used 25 years back.
Is it possible to do it in controller? Can Analog Devices DDS AD9837/9838 be used?

Thanks
PAD

[FvM]

There are many ways to achieve the intended function, starting with a pure analog solution (bandpass + amplitude regulation). Hardware DDS, processor based DDS, etc.

The solution presented in your initial post apparently suffers from limited PIC16 processing power, in my view a way to make your life harder than necessary. It doesn't sound resaonable to save 50 cents for processor hardware and compensate it with 10 $ per unit development effort and bad performance.

In most applications with 50/60 Hz signal processing I'm aware of (grid connected inverters, active front ends, PFC), the grid reference signal is required in the digital domain, not as a reconstructed analog signal. This changes things a lot, because sampling frequencies are defined by other system parameters rather than analog THD specifications. But the problem is similar, I think.

As a final remark, using zero crossing as phase reference isn't very accurate and possibly unstable in case of distorted voltage waveforms and switching interferences. It should better refer to the phase of the 50 Hz fundamental. An all-digital PLL with a multiplier phase detector can be expected to give best phase accuracy. Alternatively, a bandpass filter before the phase detector can suppress harmonics and interferences, but it has to be designed for zero phase shift.

[Mike Walne]

Sounds like you're trying to create a PFC front end.

The system I quoted was for that purpose. I ommited that the D2A used a variable reference, so the sine wave amplitude was made to match the expected load dependant current.

What are you trying to achieve?

1) If it's sinusoidal input current, yes OK.
2) If it's maximum power factor, you're going about it the wrong way.

You can't achieve perfectly stabilised output voltage from a single phase source.

Think about it. Suppose power factor was exactly unity. Then input power is sinusoidal (~ish) at twice line frequency. Therefore power into storage capacitor is also sinusoidal. If load is constant then there will inevitably be a ripple on the storage capacitor at twice line frequency.

Mike

[SherpaDoug]

Getting 1% jitter in phase from just zero crossing is going to be hard with realistic waveforms. Better would be to subtract the two waveforms and integrate (sum over one cycle). Then adjust phase until the result becomes zero.

This really looks like a "numerically controlled oscillator" project. http://en.wikipedia.org/wiki/Numerically_controlled_oscillator
_________________
The search for better is endless. Instead simply find very good and get the job done.

[asmboy]

Is there an elephant in this room??

by which i mean,
what is the defined behavior of your signal generator when going from the state of being locked to a stable reference source, when said source disappears or becomes UNSTABLE ??

thats what i mean by by an elephant ....

in my practice, the challenges are not from what is going as intended, but rather by what happens when things fail.

and for your intended use , my focus has shifted to that aspect.

You should also know that a high accuracy zero cross detector is not easy, as sherpadoug seems to also be very aware of. I second that with strong emphasis, especially concerning peak cycle to cycle AND long term "slicer"drift, if using comparators.....

[Ttelmah]

Yes. The most accurate way is to use a PLL. Once you have this, it is much easier to do the whole synthesis from this, than to use a PIC....

Best Wishes

[FvM]

[Ttelmah]

Agreed.
If he needs to be working in the digital domain for the 'next step', then a DsPIC, would indeed be the logical step.

Best Wishes

[pad]

Thanks everyone for valuable thoughts.
I am using the 1V ref. sine to multiply fundamental current(from peak detector) so that I get fundamental current which will give phase shift error from load current.
I am controlling output with 30A relay so if there is any problem in input detection circuit(supervisory code) I can cut off output.
I am now working on MC14046 PLL ,PIC16F72 & MCP4821.Currently able to call 22 sample of LUT(1.1khz VCO frequency).Very slow & bad output. and PLL frequency adjustment required lot of trial & error.
I think I need to follow your instruction of using dsPIC but its development will take more time.I am user of low/mid range PICs.
Any way, thanks all you again for giving me some of your important time.

[Ttelmah]

As a comment on the original approach, if your '167uSec', is being timed by (say) Timer2, then instead of dropping a sample, consider decreasing the period by 1 count, or increasing by one count if you want a slower output.

Best Wishes

[Mike Walne]

You've still not told us what you're doing all this for.

Mike

[SherpaDoug]