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CoderXY
Joined: 04 May 2016
Posts: 7
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| CLC configured as D-FlipFlop frequency divider(Solved) |
 Posted: Wed May 04, 2016 8:33 am |
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Hi,
I have problem getting 2 input D- Flip-Flop configured as frequency divider on 16F1507 and 12F1501 in Proteus 8.2 using CCS which is not working very well.
However using MPLABX XC8 i was able to get CLC to function as a frequency divider in Proteus.
It's just inverted output of 2 input D-Flip-Flop connected to D input.
I am using CCS PIC C compiler version 5.056.
I have attached code below.
Please help me in getting this basic 2 D-Flip-Flop to function as frequency divider using CCS.
The output seems to produce inconsistent frequency.
I do suspect there is a possible bug in CCS.
My main objective is to use 16F18325 and configure CLC as divide by 3.
Similar to CD4017 configured as divide by 3.
| Code: |
#include <12F1501.h>
#fuses NOWDT,NOMCLR,NOPROTECT
#use delay(internal=4MHz)
void main(){
setup_port_a(NO_ANALOGS);
// setup_comparator( NC_NC);
setup_adc_ports( NO_ANALOGS );
setup_adc( ADC_OFF );
// setup_clc2(CLC_ENABLED | CLC_OUTPUT|CLC_MODE_2_INPUT_D_FLIP_FLOP);
setup_clc2(CLC_ENABLED | CLC_OUTPUT | CLC_MODE_2_INPUT_D_FLIP_FLOP);
clc2_setup_input(1,CLC_INPUT_0);
// clc2_setup_input(1,CLC_INPUT_0); //assign CLC2IN0 as input 1
clc2_setup_input(4,CLC_OUTPUT_INVERTED); //assign inverted CLC2 output as input 4
// clc2_setup_gate(1,0x102); //assign input 1 to gate 1 .Input 1 is inverted
// clc2_setup_gate(2,0x180); //assign input 4 to gate 2 .Input 2 is inverted
clc2_setup_gate(1,0x002); //assign input 1 to gate 1
clc2_setup_gate(2,0x080 ); //assign input 4 to gate 2
clc2_setup_gate(3,CLC_GATE_CLEAR); //assign a low level to gate 3
clc2_setup_gate(4,CLC_GATE_CLEAR); //assign a low level to gate 4
while(TRUE) {
}
}
//extracted from MPLABX for PIC16F1507 using CLC2
// CLC2POL = 0x00;
// LC2D2S LC2OUT; LC2D1S CLCIN0;
// CLC2SEL0 = 0x50;
// LC2D4S CLCIN0; LC2D3S LC1OUT;
// CLC2SEL1 = 0x40;
// LC2G1D3N disabled; LC2G1D2N disabled; LC2G1D4N disabled; LC2G1D1T enabled; LC2G1D3T disabled; LC2G1D2T disabled; LC2G1D4T disabled; LC2G1D1N disabled;
// CLC2GLS0 = 0x02;
// LC2G2D2N enabled; LC2G2D1N disabled; LC2G2D4N disabled; LC2G2D3N disabled; LC2G2D2T disabled; LC2G2D1T disabled; LC2G2D4T disabled; LC2G2D3T disabled;
// CLC2GLS1 = 0x04;
// LC2G3D1N disabled; LC2G3D2N disabled; LC2G3D3N disabled; LC2G3D4N disabled; LC2G3D1T disabled; LC2G3D2T disabled; LC2G3D3T disabled; LC2G3D4T disabled;
// CLC2GLS2 = 0x00;
// LC2G4D1N disabled; LC2G4D2N disabled; LC2G4D3N disabled; LC2G4D4N disabled; LC2G4D1T disabled; LC2G4D2T disabled; LC2G4D3T disabled; LC2G4D4T disabled;
// CLC2GLS3 = 0x00;
// LC2EN enabled; LCINTN disabled; LCINTP disabled; LC2MODE 2-input D flip-flop with R; LC2OE enabled;
// CLC2CON = 0xC5; |
Last edited by CoderXY on Sat May 07, 2016 6:06 am; edited 1 time in total |
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temtronic
Joined: 01 Jul 2010
Posts: 9241
Location: Greensville,Ontario
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| Posted: Wed May 04, 2016 10:38 am |
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re:...
in Proteus 8.2 using CCS which is not working very well.
You've answered your own question !!! Please read the sticky PIC101.
Proteus(in all versions) is KNOWN to be buggy, flawed, faulty DRCs....
Get a REAL PIC, program it and see what happens in the real World.
Jay |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Wed May 04, 2016 10:52 am |
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I have a question. This stuff at the bottom, such as:
| Quote: | //extracted from MPLABX for PIC16F1507 using CLC2
// CLC2POL = 0x00;
// LC2D2S LC2OUT; LC2D1S CLCIN0;
// CLC2SEL0 = 0x50;
// LC2D4S CLCIN0; LC2D3S LC1OUT;
// CLC2SEL1 = 0x40;
etc.
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Is this the CLC registers setup that is produced by XC8 and it works ?
In other words, if you could duplicate that register setup with CCS would
that produce a working program ?
If true, then all you have to do is to look at the CCS .LST file in Symbolic
mode, so you can see the register names. Then play around with the
function parameters and re-compile until you get the same values loaded
into the CLC registers as shown above. |
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CoderXY
Joined: 04 May 2016
Posts: 7
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| Posted: Wed May 04, 2016 4:26 pm |
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| PCM programmer wrote: | I have a question. This stuff at the bottom, such as:
| Quote: | //extracted from MPLABX for PIC16F1507 using CLC2
// CLC2POL = 0x00;
// LC2D2S LC2OUT; LC2D1S CLCIN0;
// CLC2SEL0 = 0x50;
// LC2D4S CLCIN0; LC2D3S LC1OUT;
// CLC2SEL1 = 0x40;
etc.
|
Is this the CLC registers setup that is produced by XC8 and it works ?
In other words, if you could duplicate that register setup with CCS would
that produce a working program ?
If true, then all you have to do is to look at the CCS .LST file in Symbolic
mode, so you can see the register names. Then play around with the
function parameters and re-compile until you get the same values loaded
into the CLC registers as shown above. |
Hi PCM programmer,
I have extracted the assembly code from the .LST file and
transported to CCS PIC C.
I have post link to image at the bottom to show using assembly exported from MPLABX XC8 .LST file to reveal it "work as intended" in Proteus 8.2 .
16f1507 clc2 configured as 2 input D-Flip-Flop(Frequency divider)- 12khz input 6khz output.
I have also attached 2nd image to show inconsistent waveform to reveal using the CLC2 CCS setup did not work as expected
shown at the last few lines of code
Please help me to solve the CCS PIC C CLC setup issue.
The result was the same using CCS PIC C for 16f1507 or 12f1501 (older chip) with single CLC feature.
I do suspect there is issue with one of the CLC logic gate which was not setup correctly in CCS pic c.
| Code: |
#include <16F1507.h>
#fuses NOWDT,NOMCLR,NOPROTECT
#use delay(internal=4Mhz)
void main(){
SET_TRIS_C(0xFE); //This 1 line replace the assembly code pin Initialize below
#asm
//PIN_MANAGER_Initialize
//movlb 2 ; select bank2
//clrf 13 ;volatile
//clrf 12 ;volatile
//clrf 14 ;volatile
//movlw 23
//movlb 3 ; select bank3
//movwf 12 ;volatile
//movlw 48
//movwf 13 ;volatile
//movlw 198
// movwf 14 ;volatile
// movlw 63
// movlb 4 ; select bank4
// movwf 12 ;volatile
// movlw 240
// movwf 13 ;volatile
// movlb 1 ; select bank1
// movwf 13 ;volatile
// movlw 254
// movwf 14 ;volatile
// movlw 63
// movwf 12 ;volatile
// bsf 21,7 ;volatile
// movlb 2 ; select bank2
// clrf 29 ;volatile
// bcf 11,3 ;volatile
;pin_manager.c: 63: OPTION_REGbits.nWPUEN = 0x1;
bsf 21,7 ;volatile //1 line extracted from above assembly code ***required*
// CLC2_Initialize as 2 input Flip-Flop and inverted output of Flip-Flop to D Flip-Flop input
;clc2.c: 63: CLC2POL = 0x00;
movlb 30 ; select bank30
clrf 25 ;volatile
;clc2.c: 66: CLC2SEL0 = 0x50;
movlw 80
movwf 26 ;volatile
;clc2.c: 69: CLC2SEL1 = 0x40;
movlw 64
movwf 27 ;volatile
;clc2.c: 72: CLC2GLS0 = 0x02;
movlw 2
movwf 28 ;volatile
;clc2.c: 75: CLC2GLS1 = 0x04;
movlw 4
movwf 29 ;volatile
;clc2.c: 78: CLC2GLS2 = 0x00;
clrf 30 ;volatile
;clc2.c: 81: CLC2GLS3 = 0x00;
clrf 31 ;volatile
;clc2.c: 84: CLC2CON = 0xC5;
movlw 197
movwf 24 ;volatile
#endasm
// setup_clc2(CLC_ENABLED | CLC_OUTPUT | CLC_MODE_2_INPUT_D_FLIP_FLOP);
// clc2_setup_input(1,CLC_INPUT_0); //assign CLC2IN0 as input 1
// clc2_setup_input(4,CLC_OUTPUT_INVERTED); //Inverted output of flip-flop to input 4
// clc2_setup_gate(1,0x002); //assign input 1 to gate 1
// clc2_setup_gate(2,0x080 ); //assign input 4 to gate 2
// clc2_setup_gate(3,CLC_GATE_CLEAR); //assign a low level to gate 3
// clc2_setup_gate(4,CLC_GATE_CLEAR); //assign a low level to gate 4
while(TRUE) {
}
}
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http://pasteboard.co/GJIoS3U.jpg
http://pasteboard.co/GJym3dc.jpg |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19535
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| Posted: Thu May 05, 2016 4:00 am |
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You are trying to use the wrong defines in instructions. Look at the include file. You will see (for example), that the only parameter supported for setup_input, is the input define. You are trying to use the output define here. In the CCS version, you setup the input source _only_ with this instruction, and then define what this source connects to elsewhere.
The CCS method, actually matches the data sheet (somebody must have been having a bad day!...). You select the input source to feed to each of the four input connections (you don't select polarity here), then you gate these to the CLC, then you select the logic function required for the CLC. Quite logical.
Beware also, that _all_ data gating, is specifically listed as 'undefined at power up', so you must set all four gates, not just two. The inversion is done by using the NOR in the gate selection, with the second input selected as 0.
The register values you have for the 1507, won't directly work for the 1501. The input selections on the later chip are much more restrictive, and use different numbers for the source selected.
So:
| Code: |
// LC2D2S LC2OUT; LC2D1S CLCIN0;
// CLC2SEL0 = 0x50;
// LC2D4S CLCIN0; LC2D3S LC1OUT;
// CLC2SEL1 = 0x40;
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Is actually selecting LC2 out for the first input, and LC1OUT for the second. However you have then omitted the CLC2SEL2 and CLC2SEL3 registers which define the third and fourth inputs on this chip. On this six bits are used to select each input (32 choices).
On the 1501, there are only the two registers, but just four bits are used for each. So the CCS selections for these two are:
| Code: |
//First you perform data selection.
clc2_setup_input(1,0); //disable first input
clc2_setup_input(2,CLC_INPUT_0); //In 0 pin
clc2_setup_input(3,0); //disable third input
clc2_setup_input(4,CLC_INPUT_4); //assign LC1 output as input 4
//look at table 22-1, for why this is the selection required. LC1 out
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Now you have four inputs defined into the first part of the logic.
Then you setup the gating. You want 'OR' for the first gate, and NOR for the second, and disabling the two unused gates
The gating actually specifies whether you are using the inverted or non inverted selections. The gates are just AND gates. If you invert both the inputs and outputs you get OR
:
| Code: |
//Then gating
clc2_setup_gate(1,CLC_GATE_CLEAR); //0 output
clc2_setup_gate(2,CLC_GATE_OR & 8); //assign input 2 to this directly
clc2_setup_gate(3,CLC_GATE_CLEAR); //0 from the third gate
clc2_setup_gate(4,CLC_GATE_NOR & 0x80); //Assign input 4 and invert
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Here you use the function required, and the pins to feed 'into' this function.
Then finally you setup the logic required:
| Code: |
//Then logic function selection
setup_clc2(CLC_ENABLED | CLC_OUTPUT | CLC_MODE_2_INPUT_D_FLIP_FLOP);
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I think this should be close to right, but haven't got a 1501 to play with at the moment. However I looked at the logic when the feature first appeared in CCS, and this is how I worked it out. |
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temtronic
Joined: 01 Jul 2010
Posts: 9241
Location: Greensville,Ontario
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| Posted: Thu May 05, 2016 5:08 am |
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I'd have thought CCS would have an example for the 'CLC' PICs but my compiler versions are rather old.....
If not, ask and they will probably do one for the next release ?
Jay |
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CoderXY
Joined: 04 May 2016
Posts: 7
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| Posted: Thu May 05, 2016 9:07 am |
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| temtronic wrote: | I'd have thought CCS would have an example for the 'CLC' PICs but my compiler versions are rather old.....
If not, ask and they will probably do one for the next release ?
Jay |
hi temtronic,
I have tried out the code you gave but it did not work at all.
I did modify later on but it did not work as well.
There was a example provided by CCS PIC C somewhere but it's related to Inverted AND gates.
I hope someone can provide a solution using CCS PIC C to create a working 2 input D- Flip-Flop.
Only the assembly version works as shown previously. 
I would be using 16f1765(3 CLC) or 16f18325(4 CLC) to function as divide by 3 and it's output is PWM with appropriate dead-time between gaps.
My discrete circuit using TLC272(Op-Amp)->74HC14->4017(Div by 3)
then connected to 74HC14 to expand the signal to around 50% then it's output connected to IR2184->then to 2 IGBT.
(Parametric oscillator experiment) |
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RF_Developer
Joined: 07 Feb 2011
Posts: 839
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| Posted: Thu May 05, 2016 9:27 am |
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| Quote: |
I hope someone can provide a solution using CCS PIC C to create a working 2 input D- Flip-Flop.
Only the assembly version works as shown previously. |
You do mean working in hardware, not in Proteus? I ask because it's possible it only worked in Proteus.
And what, exactly, is a "2 input" D-type? D-type flip-flops have a clock input, a data input, a pair, inverted and non-inverted outputs, and can also have set and clear inputs. A simple divider would normally have the inverted output wired back to the data input, and the clear would often be used to implement a reset function. All that you need is a single input to the clock and pick the output of one of the outputs, which depending on the phase of the required signal.
All a divide by three is is a counter whish has it's output decoded to reset the count after three states: 00, 01 and 10. Runt pulses and full-on glitches can be a siginifcant issue with naive designs. Decoded decade counters such as the 4017 often use synchronous counters internally rather than ripple counters made from D-types. |
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CoderXY
Joined: 04 May 2016
Posts: 7
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| Posted: Thu May 05, 2016 10:26 am |
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| RF_Developer wrote: | | Quote: |
I hope someone can provide a solution using CCS PIC C to create a working 2 input D- Flip-Flop.
Only the assembly version works as shown previously. |
You do mean working in hardware, not in Proteus? I ask because it's possible it only worked in Proteus.
And what, exactly, is a "2 input" D-type? D-type flip-flops have a clock input, a data input, a pair, inverted and non-inverted outputs, and can also have set and clear inputs. A simple divider would normally have the inverted output wired back to the data input, and the clear would often be used to implement a reset function. All that you need is a single input to the clock and pick the output of one of the outputs, which depending on the phase of the required signal.
All a divide by three is is a counter whish has it's output decoded to reset the count after three states: 00, 01 and 10. Runt pulses and full-on glitches can be a siginifcant issue with naive designs. Decoded decade counters such as the 4017 often use synchronous counters internally rather than ripple counters made from D-types. |
hi RF_Developer,
The prototype using handful of discrete components is working according to my requirement.But i wanted to use Microchip to prevent reverse engineering.
Proteus is merely used to quickly test logic gates and short codes like CLC configured as Flip-Flop. It does save me time instead of removing chip from programmer ZIF socket to test circuit.
Alternative to 4017 those D-FF(need 3) can be easily configured as divide
by 3.Using additional AND logic gates connected to inverted Q or 1st and 2nd FF and output back to 1st FF.OR Gate to 2nd and 3rd Q of FF which will be the output.
I understand Microchip CLC is a new thing there is hardly any examples in the net which hardly uses CCS C.
I sincerely do hope someone can assist to solve this CLC issue in CCS C.
The reason i used older chip in virtual environment because MPLABX MCC ->CLC don't work for new i/c like 16f18325 and 16F1765. |
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temtronic
Joined: 01 Jul 2010
Posts: 9241
Location: Greensville,Ontario
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| Posted: Thu May 05, 2016 2:22 pm |
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If you can't get the CLC stuff to run right, just program the PIC using CCS C ! 2 decades ago I used a PIC16C84 as a 'PLC' in some custom kit to foil( well slow down) the reverse engineers.
Microchip does have an application note on using PICs as PLCs. Yeah, it'll be old ( like 20 years) BUT it might give you a viable option.
Jay |
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CoderXY
Joined: 04 May 2016
Posts: 7
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| Posted: Thu May 05, 2016 6:16 pm |
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| temtronic wrote: | If you can't get the CLC stuff to run right, just program the PIC using CCS C ! 2 decades ago I used a PIC16C84 as a 'PLC' in some custom kit to foil( well slow down) the reverse engineers.
Microchip does have an application note on using PICs as PLCs. Yeah, it'll be old ( like 20 years) BUT it might give you a viable option.
Jay |
hi temtronic,
The reason why CLC is so cool because it is not dependent on the Microchip core clock.
The internal multiplexer part of CLC once set will allow the i/c-CLC to function in real time even if the core is running at 32khz.
At the current moment only one useful document related to programming CLC is found here-
http://musiccolor.d-lan.dp.ua/Microchip/masters2013/classes/17013.pdf |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19535
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| Posted: Fri May 06, 2016 1:56 am |
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That is only really an expansion of what is in the data sheet.
Key thing is to draw out the actual logic you want.
The CCS approach follows exactly the data sheet description. All they omit to tell you is that you have to add in the bits needed for the CLCSEL registers, to the setup_gate calls.
Now to program a /2, using CCS (ignoring everything else), you want a 2 input flip flop, with it's D input fed from /Q, no reset, and a clock from the external input pin.
Looking at Table 22-1, this shows that IC2D1 can select CLC2IN0 with selection 0. IC2D3 can select IC2_OUT, with selection 1. So use these. Then the 2 input F-F, requires clock on ICXG1, D from ICXG4 OR ICXG2, and reset is ICXG3. So set ICXG3 = 0. ICXG4 = 0, and feed ICXG2 with the inverted output, and ICXG1 with the clock input:
| Code: |
clc2_setup_input(1,CLC_INPUT_0); //CLC2IN0
clc2_setup_input(2,0); //DISABLE
clc2_setup_input(3,CLC_INPUT_1); //IC2_OUT
clc2_setup_input(4,0); //DISABLE
//look at table 22-1, for why this is the selection required. LC1 out
//Now the bit patterns needed are:
//0b00000001 //first gate
//0b00100000 //second gate - inverted from third input - /IC2_OUT
//other not used
//Then gating
clc2_setup_gate(1,1); //CLOCK Input
clc2_setup_gate(2,0x20); //generate Q/
clc2_setup_gate(3,CLC_GATE_CLEAR); //0 from the third gate
clc2_setup_gate(4,CLC_GATE_CLEAR); //0 from fourth
//Then logic function selection
setup_clc2(CLC_ENABLED | CLC_OUTPUT | CLC_MODE_2_INPUT_D_FLIP_FLOP);
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That should give a flip flop from the CLC2IN0 pin, outputting /2. |
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CoderXY
Joined: 04 May 2016
Posts: 7
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| Posted: Fri May 06, 2016 3:17 am |
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| Ttelmah wrote: | That is only really an expansion of what is in the data sheet.
Key thing is to draw out the actual logic you want.
The CCS approach follows exactly the data sheet description. All they omit to tell you is that you have to add in the bits needed for the CLCSEL registers, to the setup_gate calls.
Now to program a /2, using CCS (ignoring everything else), you want a 2 input flip flop, with it's D input fed from /Q, no reset, and a clock from the external input pin.
Looking at Table 22-1, this shows that IC2D1 can select CLC2IN0 with selection 0. IC2D3 can select IC2_OUT, with selection 1. So use these. Then the 2 input F-F, requires clock on ICXG1, D from ICXG4 OR ICXG2, and reset is ICXG3. So set ICXG3 = 0. ICXG4 = 0, and feed ICXG2 with the inverted output, and ICXG1 with the clock input:
| Code: |
clc2_setup_input(1,CLC_INPUT_0); //CLC2IN0
clc2_setup_input(2,0); //DISABLE
clc2_setup_input(3,CLC_INPUT_1); //IC2_OUT
clc2_setup_input(4,0); //DISABLE
//look at table 22-1, for why this is the selection required. LC1 out
//Now the bit patterns needed are:
//0b00000001 //first gate
//0b00100000 //second gate - inverted from third input - /IC2_OUT
//other not used
//Then gating
clc2_setup_gate(1,1); //CLOCK Input
clc2_setup_gate(2,0x20); //generate Q/
clc2_setup_gate(3,CLC_GATE_CLEAR); //0 from the third gate
clc2_setup_gate(4,CLC_GATE_CLEAR); //0 from fourth
//Then logic function selection
setup_clc2(CLC_ENABLED | CLC_OUTPUT | CLC_MODE_2_INPUT_D_FLIP_FLOP);
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That should give a flip flop from the CLC2IN0 pin, outputting /2. |
hi Ttelmah,
I have tested your provided code but it was not working.
From your code i got an idea and tried manually connecting LC2OUT to inverted input at CLC_INPUT_1 (RC4 pin 6) .
It did not work as well.It produce the usual inconsistent waveform.
#include <16F1507.h>
#fuses NOWDT,NOMCLR,NOPROTECT,NOBROWNOUT,NOPUT,NOCLKOUT,NOSTVREN
#use delay(internal=4MHz)
void main(){
clc2_setup_input(1,CLC_INPUT_0); //CLC2IN0
clc2_setup_input(2,0); //DISABLE
clc2_setup_input(4,CLC_INPUT_1); //IC2_OUT
clc2_setup_input(3,0); //DISABLE
//look at table 22-1, for why this is the selection required. LC1 out
//Now the bit patterns needed are:
//0b00000001 //first gate
//0b00100000 //second gate - inverted from third input - /IC2_OUT
//other not used
//Then gating
clc2_setup_gate(1,CLC_GATE_OR & 0x002); //CLOCK Input
clc2_setup_gate(2,CLC_GATE_OR & 0x000); //generate Q/
clc2_setup_gate(3,CLC_GATE_OR & 0x000); //0 from the third gate
clc2_setup_gate(4,CLC_GATE_OR & 0x180); //0 from fourth .Invert input instead of output set using "1"
//Then logic function selection
setup_clc2(CLC_ENABLED | CLC_OUTPUT | CLC_MODE_2_INPUT_D_FLIP_FLOP);
while(TRUE) {
}
} |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19535
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| Posted: Fri May 06, 2016 4:40 am |
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You are slightly misunderstanding the CLC input selections.
Look at table 22-1.
The eight selections CCS call 'CLC_INPUT_0', 'CLC_INPUT_1' etc..
What these physically connect 'to', depends on which ICXG input you are using.
CLC_INPUT_1 on ICXG3, connected to IC2_OUT. Nothing to do with the CLC input pin.
The way to work it out, is to start much simpler. Forget the flip-flop, and set the logic to give CLC_GATE_OR. Disable all but gate 1, (CLC_GATE_CLEAR on the other gates) and then see if you have the input signal coming out on the logic output.
Then feed another input pin in, and verify that you can invert this, by selecting one bit higher on the bit patterns. These work as:
| Code: |
ICXG1
/ICXG1
ICXG2
/ICXG2
ICXG3
/ICXG3
ICXG4
/ICXG4
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These are the bits across the byte from bit 0 to bit 7.
So if you want the gate to receive just the bottom ICXG1 signal you select '1'. If you want it to have the inverted signal, you select '2'. If however you want it to have all the non inverted signals, you select 0x55, while for all the inverted signals, 0xAA.
Each gate bit is AND'ed, with the corresponding ICXG signal, and the output of this feeds into an OR gate, who's output then feeds into an XOR with it's other input from the corresponding 'POL' bit.
So (for instance), selecting:
clc2_setup_gate(1,1); //CLOCK Input
Feeds the ICXD1T signal into ICXG1.
Selecting:
clc2_setup_gate(1,0x101); //CLOCK Input
Inverts the gate output.
clc2_setup_gate(1,2); //CLOCK Input
Instead feeds the inverted input into the gate.
Obviously with only a single input selected, these both give the same result, but if you were feeding in multiple inputs, you could invert both the inputs and the outputs to give AND, instead of OR. Then by choosing to invert the output, you could have NAND, and NOR.
So try some simpler logic first and verify that you can feed a signal into the right pin, and get inverted or non-inverted outputs.
The code as programmed wants it's input on CLC2IN0 (RA1). The output should be on CLC2 (RA5). |
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CoderXY
Joined: 04 May 2016
Posts: 7
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| Posted: Fri May 06, 2016 6:09 am |
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hi everyone,
This is my final contributed version of the pic16f1507 CLC2 setup as 2-Input D-FLIP-FLOP which is configured as frequency divider.
Signal generator to pin RC3 28khz and output from pin RC0 14khz.
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//PIC16F1507 CLC2 using 2 input D- Flip-Flop and configured as frequency divider (1/2)
#include <16F1507.h>
#fuses NOWDT,NOMCLR,NOPROTECT,NOBROWNOUT,NOPUT,NOCLKOUT,NOSTVREN
#use delay(internal=4MHz) //Core clock don't get involved with CLC.CLC works real-time
void main(){
setup_clc2(CLC_ENABLED | CLC_OUTPUT | CLC_MODE_2_INPUT_D_FLIP_FLOP);
clc2_setup_input(1,CLC_INPUT_0); //assign CLC2IN0 as input 1
clc2_setup_input(2,CLC_INPUT_5); //Q flip-flop is inverted at input 'D'
clc2_setup_gate(1,0x02); //assign input 1 to gate 1
clc2_setup_gate(2,0x04 ); //assign input 2 to gate 2
clc2_setup_gate(3,CLC_GATE_CLEAR); //assign a low level to gate 3
clc2_setup_gate(4,CLC_GATE_CLEAR); //assign a low level to gate 4
while(TRUE)
{
}
}
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