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Three phase PWM for AC motor with PIC18F4431
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Scarface



Joined: 03 Dec 2013
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Three phase PWM for AC motor with PIC18F4431
PostPosted: Tue Dec 31, 2013 11:17 am     Reply with quote

Hi,
I'm making a project using pic18f4431 which drive three phase ac motor. I put pwm outputs in complimentary mode and everything is OK. But to drive the ac motor I need 120 degree offset between each inverter arm. So, can someone help me with code?
Code:
#include <18F4431.h>
#fuses INTRC_IO,NOWDT,PUT,BROWNOUT,NOLVP
#use delay(clock=8M)
#define POWER_PWM_PERIOD 40  // Gives 25 KHz pwm freq with PWM_CLK_DIV_4
   

void main()
   {
   float adc_val;

   setup_power_pwm_pins(PWM_COMPLEMENTARY,PWM_COMPLEMENTARY,PWM_COMPLEMENTARY,PWM_OFF);
   setup_power_pwm(PWM_UP_DOWN | PWM_CLOCK_DIV_4 |  PWM_DEAD_CLOCK_DIV_2, 1, 0, POWER_PWM_PERIOD, 0, 1, 0);

   setup_adc_ports(sAN1);   
   setup_adc(ADC_CLOCK_INTERNAL | ADC_CONT_A | ADC_WHEN_PPWM);
   while(TRUE)
      {     
      set_adc_channel(1);
      delay_us(1);
      adc_val = read_adc();
   
      set_power_pwm0_duty((int16)((POWER_PWM_PERIOD *4) * (adc_val/255)));
      set_power_pwm2_duty((int16)((POWER_PWM_PERIOD *4) * (adc_val/255)));
      set_power_pwm4_duty((int16)((POWER_PWM_PERIOD *4) * (adc_val/255)));
      }
    }

Best Regards!
Mike Walne



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PostPosted: Tue Dec 31, 2013 12:26 pm     Reply with quote

We need lots more information about what you are trying to do.

1) What is the adc reading supposed to control?
2) Are you wanting to control motor speed?
3) What have you already tried?
4) What searches have you done?
5) ...............................

Mike
temtronic



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PostPosted: Tue Dec 31, 2013 12:39 pm     Reply with quote

There's a Microchip application note about doing it ! Had it on my desktop..opened it ,read a bit then ..decided to clean up the PC...now it's in 'some folder, somewhere' on this silly PC. Shouldn't be too hard to find at the uChip site though,faster than me trying to figure out just where I put it this morning.

hth
jay


+++++++++++++++++
Jay,
A reminder. Give a useful answer - not that you lost an appnote.
It's a help forum. Not a chat forum.

- Forum Moderator
+++++++++++++++++
Scarface



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PostPosted: Tue Dec 31, 2013 4:52 pm     Reply with quote

Mike,
adc reading in code is for variable speed control. The idea in this project is exactly motor speed control. I have also current,voltage and temperature feedbacks and LCD display and there is no problem to write their source code. I want to generate three phase pwm which will drive my ac motor. What I've done is to set pwm in complimentary mode (T1, T3, T5-high; T2, T4, T6-low), but this iя not correct for three phase inverter - all pwms have same phase angle. So I need 120 degree offset between each inverter arm. I read CCS manual but I don't find any function for this.

T1....T3....T5
.|......|......|.
T2....T4....T6

Applications which I use are:
AC Induction Motor Fundamentals http://ww1.microchip.com/downloads/en/AppNotes/00887a.pdf
Controlling 3-Phase AC Induction Motors Using the PIC18F4431 http://ww1.microchip.com/downloads/en/AppNotes/00900a.pdf
Ttelmah



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PostPosted: Wed Jan 01, 2014 2:11 am     Reply with quote

The point about Jay's post, is that there _is_ an app note.
He has lost it, but is pointing out that a quick search of the MicroChip site should find it, and this ought to be the starting point.

I think it is probably AN900 that he is thinking of (there are actually quite a few more for more complex control), which the original poster has already found.

In general the 'flowchart' of such notes gives a great key to how it needs to be done.

However I think there is a fundamental misunderstanding about how you do this from the original poster. You don't use the pulses of the PWM to directly drive the individual phases with just on/off. You synthesise a sinusoidal waveform by varying the mark/space of the PWM. You run the PWM, at something like 10KHz, and are changing the value fed to each of the three outputs on every cycle of this. Study how AN900 updates the pwm ratios....

Best Wishes
Mike Walne



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PostPosted: Wed Jan 01, 2014 3:42 am     Reply with quote

Having found AN900 you need to read it carefully.

Ttelmah has drawn attention to the fundamental error in your understanding of what's required.

Each of the PWMs is varied to synthesise a sine wave.
It's these three sine wave which are 120 degrees out of step with each other.
The principal determinant of motor speed is the frequency of the sine waves, not the PWM ratio as you seem to think.

It's all in the app note.

Happy new year.

Mike
Scarface



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PostPosted: Wed Jan 01, 2014 6:28 am     Reply with quote

I know that synthesise a sinusoidal waveform is by varying the space of the PWM. Varying duty cycle of PWM I control sine waves and respectively induction motor. But to work three phase inverter you not have to allow transistors T1,T3,T5 or T2,T4,T6 to work at the same time. If they work at the same time they will burn. What I mean by wanting to put PWM offset like a picture I posted you can see this in this app http://www.tntech.edu/files/cesr/StudThesis/asuri/Chapter4.pdf . App explains fundamental princip of inverters. Look at from point 4.3 three phase inverter to the end of pdf and you'll understand what I want to do.
PCM programmer



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PostPosted: Wed Jan 01, 2014 7:39 am     Reply with quote

Search the Microchip forum. Use Google to search for this:
Quote:
site:microchip.com/forums 3-phase pwm 18F4431 OR 18F2431 OR 18F4331 OR 18F2331
Ttelmah



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PostPosted: Wed Jan 01, 2014 7:59 am     Reply with quote

The only FET's that mustn't/won't be on at the same time, are the second one in each pair. So, using the numbers from Fig1, in AN900, PWM2 must not be on at the same time as PWM1. Similarly 2/3, and 4/5. However PWM3, and PWM1, _will_ be on at the same time, as will PWM1, and PWM4, at different parts of the cycle etc..
The point is that the individual PWM waveforms _won't_ display the relationship you are looking for. It is the combined 'effect' out, from the selection of mark/space ratio and which pairs are being driven, which has the 120 degree relationship....

Best Wishes
Mike Walne



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PostPosted: Wed Jan 01, 2014 8:22 am     Reply with quote

Scarface wrote:
I know that synthesise a sinusoidal waveform is by varying the space of the PWM. Varying duty cycle of PWM I control sine waves and respectively induction motor. But to work three phase inverter you not have to allow transistors T1,T3,T5 or T2,T4,T6 to work at the same time. If they work at the same time they will burn. What I mean by wanting to put PWM offset like a picture I posted you can see this in this app http://www.tntech.edu/files/cesr/StudThesis/asuri/Chapter4.pdf . App explains fundamental princip of inverters. Look at from point 4.3 three phase inverter to the end of pdf and you'll understand what I want to do.

No you're wrong. Ttelmah and I are saying the same thing.

What's NOT helping is the typo in the document you're reading.

The 1st three headings in table 4.1 SHOULD be S11, S21, S31 and NOT S11, S12, S31 as shown.

Mike
Scarface



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PostPosted: Wed Jan 01, 2014 9:00 am     Reply with quote

Ok let's say that I'm wrong and you're right.
This is ASM source code used in AN900 app. As you see there is PWM offeset exactly how I want to do.
Code:
;*******************************************************************************
;UPDATE_PWM_DUTYCYCLES
;
;This routine will update the PWM duty cycle on CCPx according to the
;offset to the table with 0-120-240 degrees.
;This routine scales the PWM value from the table based on the frequency to keep V/F
;constant.
;*******************************************************************************
UPDATE_PWM_DUTYCYCLES

   movf   TABLE_OFFSET1,W         ;Load the table offset for Phase 1
   movf   PLUSW0,W            ;Use offset to access value in sine table via indirect addressing
   mulwf   FREQUENCY, W         ;Table_value X Frequency
   movff   PRODH,PDC0H_TEMP      ;Copy high product into temporary variable for PDC0H
   movff   PRODL,PDC0L_TEMP      ;Copy low product into temporary variable for PDC0L

;   movlw   0x1E               ;Add 78h (1Eh shifted left two bits), in order to prevent 0 duty cycle
;   addwf   PDC0L_TEMP, F
;   btfsc   STATUS, C
;   incf   PDC0H_TEMP, F

UPDATE_PWM2
   movf   TABLE_OFFSET2,W         ;Load the table offset for Phase 2
   movf   PLUSW0,W            ;Use offset to access value in sine table via indirect addressing
   mulwf   FREQUENCY, W         ;Table_value X Frequency
   movff   PRODH,PDC1H_TEMP      ;Copy high product into temporary variable for PDC1H
   movff   PRODL,PDC1L_TEMP      ;Copy low product into temporary variable for PDC1L
   
;   movlw   0x1E               ;Add 78h (1Eh shifted left two bits), in order to prevent 0 duty cycle
;   addwf   PDC0L_TEMP, F
;   btfsc   STATUS, C
;   incf   PDC0H_TEMP, F
   
UPDATE_PWM3
   movf   TABLE_OFFSET3,W         ;Load the table offset for Phase 3
   movf   PLUSW0,W            ;Use offset to access value in sine table via indirect addressing
   mulwf   FREQUENCY, W         ;Table_value X Frequency
   movff   PRODH,PDC2H_TEMP      ;Copy high product into temporary variable for PDC2H
   movff   PRODL,PDC2L_TEMP      ;Copy low product into temporary variable for PDC2L
   
;   movlw   0x1E               ;Add 78h (1Eh shifted left two bits), in order to prevent 0 duty cycle
;   addwf   PDC0L_TEMP, F
;   btfsc   STATUS, C
;   incf   PDC0H_TEMP, F
   
TRUNCATE_PWM123                  ;Truncate results of multiply to 10 uppermost bits
   bcf      STATUS,C            ;discarding lower two bits and right justifying
   rlcf   PDC0L_TEMP,F
   rlcf   PDC0H_TEMP,F
   rlcf   PDC0L_TEMP,F
   rlcf   PDC0H_TEMP,F
   rlcf   PDC0L_TEMP,W
   andlw   0x3
   movff   PDC0H_TEMP,PDC0L_TEMP
   movwf   PDC0H_TEMP
   
   bcf      STATUS,C
   rlcf   PDC1L_TEMP,F
   rlcf   PDC1H_TEMP,F
   rlcf   PDC1L_TEMP,F
   rlcf   PDC1H_TEMP,F
   rlcf   PDC1L_TEMP,W
   andlw   0x3
   movff   PDC1H_TEMP,PDC1L_TEMP
   movwf   PDC1H_TEMP

   bcf      STATUS,C
   rlcf   PDC2L_TEMP,F
   rlcf   PDC2H_TEMP,F
   rlcf   PDC2L_TEMP,F
   rlcf   PDC2H_TEMP,F
   rlcf   PDC2L_TEMP,W
   andlw   0x3
   movff   PDC2H_TEMP,PDC2L_TEMP
   movwf   PDC2H_TEMP

;testofPWM
;   infsnz   temp, f
;   incf   temp1, f
;   btfss   temp1, 2         ;if this bit is set temp1=4
;   goto   donewiththis
;   clrf   temp
;   clrf   temp1
;donewiththis
;   movff   temp, PDC0L_TEMP
;   movff   temp1, PDC0H_TEMP   
            
;   movlw   0x01
;   movwf   PDC0L_TEMP
;   movlw   0x00
;   movwf   PDC0H_TEMP
;   movlw   0xe8
;   movwf   PDC1L_TEMP
;   movlw   0x03
;   movwf   PDC1H_TEMP

   call   CHECK_LIMITS

   bsf      PWMCON1, UDIS      ;Disable updates to duty cycle and period
   movff   PDC0L_TEMP,PDC0L   ;Transfer temporary values into duty cycle registers
   movff   PDC0H_TEMP,PDC0H
   movff   PDC1L_TEMP,PDC1L
   movff   PDC1H_TEMP,PDC1H
   movff   PDC2L_TEMP,PDC2L
   movff   PDC2H_TEMP,PDC2H
   
   
;   movlw   0xFA
;   movwf   PDC0L
;   movlw   0x00
;   movwf   PDC0H
;   movlw   0xF4
;   movwf   PDC1L
;   movlw   0x01
;   movwf   PDC1H
;   movlw   0xEE
;   movwf   PDC2L
;   movlw   0x02
;   movwf   PDC2H
   
   bcf      PWMCON1, UDIS      ;Enable updates to duty cycle and period to update simultaneously.

   
   return   

;*******************************************************************************
;UPDATE_TABLE_OFFSET
;
;This routine Updates the offset pointers to the table after every access
;*******************************************************************************
UPDATE_TABLE_OFFSET
   btfss   FLAGS,OFFSET1_FLAG         ;If set incr. on table
   bra      DECREMENT_OFFSET1
   movlw   (SINE_TABLE_ENTRIES-1)      ;Check for the last value on the table
   cpfslt   TABLE_OFFSET1
   bra      CLEAR_OFFSET1_FLAG
   incf   TABLE_OFFSET1,F            ;Increment offset1
   bra      UPDATE_OFFSET2

CLEAR_OFFSET1_FLAG
   bcf      FLAGS,OFFSET1_FLAG

DECREMENT_OFFSET1
   dcfsnz   TABLE_OFFSET1,F            ;Decrement offset1
   bsf      FLAGS,OFFSET1_FLAG

UPDATE_OFFSET2
   btfss   FLAGS,OFFSET2_FLAG         ;If set incr. on table
   bra      DECREMENT_OFFSET2
   movlw   (SINE_TABLE_ENTRIES-1)      ;Check for the last value on the table
   cpfslt   TABLE_OFFSET2
   bra      CLEAR_OFFSET2_FLAG
   incf   TABLE_OFFSET2,F            ;Increment offset2
   bra      UPDATE_OFFSET3

CLEAR_OFFSET2_FLAG
   bcf      FLAGS,OFFSET2_FLAG

DECREMENT_OFFSET2
   dcfsnz   TABLE_OFFSET2,F            ;Decrement offset2
   bsf      FLAGS,OFFSET2_FLAG

UPDATE_OFFSET3
   btfss   FLAGS,OFFSET3_FLAG         ;If set incr. on table
   bra      DECREMENT_OFFSET3
   movlw   (SINE_TABLE_ENTRIES-1)      ;Check for the last value on the table
   cpfslt   TABLE_OFFSET3
   bra      CLEAR_OFFSET3_FLAG
   incf   TABLE_OFFSET3,F            ;Increment offset3
   return   

CLEAR_OFFSET3_FLAG
   bcf      FLAGS,OFFSET3_FLAG

DECREMENT_OFFSET3
   dcfsnz   TABLE_OFFSET3,F            ;Decrement offset3
   bsf      FLAGS,OFFSET3_FLAG
   return
;*******************************************************************************
;Initialize PCPWM
;   NOTES:
;    1)   PTPER has 12-bit resolution, 4 LSBs of PTPERH and 8 bits of PTPERL
;    2)   In edge aligned mode, PTMR reset to zero on match with PTPER
;   3)   PDC has 14-bit resolution, 6 LSBs of PDCxH and 8 bits of PDCxL
;   4)   Lower 2 bits of PDC compared to Q clocks
;
;   5)   Resolution(of duty cycle)= log((Fosc/4)/Fpwm)/log(2) = log(5Mhz/20kHz)/log(2) = 8 bits
;      so 6 LSBs of PDCxH and 2 MSBs of PDCxL will be used.
;      (for 16kHz, resolution = log(5Mhz/16kHz)/log(2) = 8 bits, also.)
;
;*******************************************************************************
INIT_PCPWM

   movlw   b'00000000'         ; PTCON0 is configured such that:
   movwf   PTCON0         ; a) Postscale value is 1:1
                        ; b) PWM time base input is Fosc/4
                        ; c) PWM time base mode is free-running for edge-aligned operation
   
   movlw   0xF9            ; PTPERL and PTPERH are set up for a 20KHz PWM frequency.      
   movwf   PTPERL         ;    PTPERH:PTPERL = ((Fosc/4)/(PWMfreq x PTMRps))-1
   movlw   0x00            ;    PTPERH:PTPERL = ((20MHz/4)/(20KHz x 1))-1 = 249d = F9h
   movwf   PTPERH         

;   movlw   0x37            ; PTPERL and PTPERH are set up for a 16KHz PWM frequency.      
;   movwf   PTPERL         ;    PTPERH:PTPERL = ((Fosc/4)/(PWMfreq x PTMRps))-1
;   movlw   0x01            ;    PTPERH:PTPERL = ((20MHz/4)/(16KHz x 1))-1 = 311d = 137h
;   movwf   PTPERH   
   
   movlw   b'01000000'         ; PWMCON0 is configured such that:
   movwf   PWMCON0         ; a) PWM0, PWM1, PWM2, PWM3, PWM4, and PWM5 are enabled for output.
                        ; b) All PWM I/O pairs are set to complimentary mode
                              
   movlw   b'00000001'         ;PWMCON1 is configured such that:
   movwf   PWMCON1            ; a) Special event trigger post-scaler is set to 1:1
                        ; b) Special event trigger occurs when time-base is counting upwards
                        ; c) Updates from duty cycle and period buffer registers are enabled.
                        ; d) Output overrides via OVDCON are synchronous to the PWM timebase.         


   movlw   b'00001010'         ;1us deadtime instead of 2us      
;   movlw   b'00010100'         ;DTCON is configured such that:
   movwf   DTCON            ; a) Clock source for dead-time is Fosc/2.
                        ; b) Dead time = Dead time value / (Fosc/2) = 2uS.                     
;   clrf   DTCON            ;DTCON for zero dead-time (relying on IRAMS cross-conduction prevention logic)                     

;   movlw   b'00000000'
   movlw   b'11111111'         ;OVDCOND is configured such that there is no output override.
   movwf   OVDCOND
   
   movlw   b'00000000'         ;OVDCONS is configured such that all PWM outputs are 0 upon power-up.
;   movlw   b'11111111'         ;OVDCONS is configured such that all PWM outputs are 1 (inactive) upon power-up.
   movwf   OVDCONS
   
   
   ;FLTA is overcurrent fault, muxed via configuration bit to RC1
   ;FLTB is overvoltage fault on RC2
;   bsf      TRISC, 1         ;Ensure that RC1 is an input
;   bsf      TRISC, 2         ;Ensure that RC2 is an input
;   movlw   b'10000000'         ;Fault A and FaultB are disabled.
;   movlw   b'10000011'         ;Fault B is disabled
   movlw   b'10010001'         ;Fault A and FaultB are enabled in catastrophic mode.
;   movlw   b'10110011'         ;FLTCONFIG is configured such that:
   movwf   FLTCONFIG         ; a) Enable fault condition on break-point for use with ICD2
                        ; b) Enable FaultA in cycle-by-cycle mode
                        ; c) Enable FaultB in cycle-by-cycle mode
                        ; d) Fault A and Fault B disable PWM channels 0 to 5
   
   movlw   0x00            ;SEVTCMPL and SEVTCMPH are clear.
   movwf   SEVTCMPL
   movlw   0x00
   movwf   SEVTCMPH

;   clrf   PDC0L            ;PDC0L, PDC1L, PDC2L, PDC3L, PDC0H, PDC1H, PDC2H, PDC3H
;   clrf   PDC1L            ;    are clear so that duty cycles are initially 0.
;   clrf   PDC2L   
;   clrf   PDC3L   
;   clrf   PDC0H   
;   clrf   PDC1H   
;   clrf   PDC2H   
;   clrf   PDC3H   


   bsf      PTCON1, PTEN      ;PTEN bit in the PTCON1 is set to enable the PWM time base.
   
;----------------------
;infinite_loop
;   goto   infinite_loop
;----------------------
   
   
   return   

This is link from microchip site where is AN900 and complete souce code https://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1824&appnote=en020394
temtronic



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PostPosted: Wed Jan 01, 2014 9:52 am     Reply with quote

comment: OK, I finally did find the apnote and it is AN900 and managed to loose 27,000+ PIC CCS files in the meantime,so I'm not exactly happy this new year...
Providing the asm code you show is compatible with your PIC, you code add it using the CCS instaruction..#asm..... something that CCS does allow and I've used in the past.
Another option is to 'decode' what it's doing and create similar C code.Good news is uChp has pretty good comments on what's going on. Yes, not exactly what a rookie programmer can easily do, but can be done,just takes some time.
Yet another option is to use additional hardware to make the 3 phase outputs.If you start with a 6* clock signal then feed that into a /6 counter, you'll get 3phases 120* apart.Sorry I don't have apart number or schematic to provide but it's an 'old school' way of doing it.You only need one PWM signal(6* desired frequency).

hth
jay
Mike Walne



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PostPosted: Wed Jan 01, 2014 11:15 am     Reply with quote

Yes. The offset is forcing each PWM channel to look up a sine table value which is 120 degrees phase shifted from the other channels.

In the microchip code all three PWM channels are being set edge aligned.
There's nothing to stop T1, T3 & T5 turning on together. Nor for that matter T2, T4 & T6.

It's important T1/2 don't turn on together, (and of course T3/4 & T5/6).

If you try to prevent T1,3,5 coming on simultaneaously you'll likely end up with a huge DC component across at least one winding with equally disastrous results.

Mike
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PostPosted: Wed Jan 01, 2014 12:46 pm     Reply with quote

Is there any way this code to be modified from ASM to CCS because I have no idea of assembler programing. Or my code to be written with offset.

The reason why T1,T3 and T5 haven't work together at the same time is because then the electrical circuit can't be closed. The Circuit always is between Power supply/Signal and ground but this case you haven't it. The second thing is that in this mode 100% you will burn out some of the electronic elements. Some is with T2,T4 and T6. I've seen blown inverters for this reason. You are right when you say that T1 and T2(3/4 or 5/6) don't be turn on together. The correct way of working is: two transistors up(T1,T3 or T5) and one down(T2,T4 or T6) or one up and two down at the same time. This is the reason why is set 120 degree offset. It keeps transistor from wrong work. You can see it and from the picture I posted.
Ttelmah



Joined: 11 Mar 2010
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PostPosted: Wed Jan 01, 2014 3:47 pm     Reply with quote

The code is not exactly hard to modify. 50% of it is remmed out, and the values are just a matter of array lookups, multiplication, and loading the registers.
The point though is that the hardware does not ensure the transistors don't overlap. It is just the code that does this.

Best Wishes
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