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epitalon
Joined: 11 Mar 2010
Posts: 11
Location: france
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| Writing to flash rom |
 Posted: Tue Jan 26, 2016 6:10 am |
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Hello all,
I use a program (supplied by CCS) that emulates EEPROM by writing data into program flash ROM.
It works as long there is no interrupt during write to flash. I realize that the problem lies in the fact that ISR does not save the TBLPTR register. The ISR corrupts TBLPTR.
I am using CCS version PCH 4.104 and PIC18F86J50.
Do one of you know of a fix to this problem ? |
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RF_Developer
Joined: 07 Feb 2011
Posts: 839
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| Posted: Tue Jan 26, 2016 7:47 am |
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Make it a critical section. In other words disable interrupts before and re-enable after.
The PIC will, in fact, be totally unresponsive during the write itself - the processor is stalled during writes to program memory. |
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epitalon
Joined: 11 Mar 2010
Posts: 11
Location: france
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| Posted: Tue Jan 26, 2016 8:17 am |
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| RF_Developer wrote: | | Make it a critical section. In other words disable interrupts before and re-enable after. |
Yes, I used that solution but I wonder if there is a fix in the compiler or a compilation option.
| RF_Developer wrote: | | The PIC will, in fact, be totally unresponsive during the write itself - the processor is stalled during writes to program memory. |
Actually, the problem occurs not during the write itself (there is no interrupt during that time since, as you say, the cpu is unresponsive). It occurs during execution of preparatory instructions, which set TBLPTR and other registers. |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19539
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| Posted: Tue Jan 26, 2016 9:25 am |
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This is a 'read the data sheet' one. If you look at (for instance), the basic flash write operation for one location in the data sheet, the sequence listed/required is:
| Code: |
1. Load the Table Pointer register with the address
of the data to be written. (It must be an even
address.)
2. Write the 2 bytes into the holding registers by
performing table writes. (Do not post-increment
on the second table write.)
3. Set the WREN bit (EECON1<2>) to enable
writes and the WPROG bit (EECON1<5>) to
select Word Write mode.
4. Disable interrupts.
5. Write 55h to EECON2.
6. Write AAh to EECON2.
7. Set the WR bit. This will begin the write cycle.
8. The CPU will stall for duration of the write for TIW
(see parameter D133A).
9. Re-enable interrupts.
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Note '4' & '9'.
All of the flash write operations _require_ interrupts to be disabled for the actual write, and the CPU will stall after the WR bit is set.
This is one thing that makes it very worthwhile using external memory, rather than the flash on these chips, since the pause is long enough to give problems if USB or fast serial is happening when a write occurs. For serial, it's vital to use flow control and stop data during the write. For USB, provided the USB is checked immediately before the write, and is not using interrupt transfers, it is OK. |
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