Dual-core dsPIC just released - dsPIC33CH

rjenkinsgb · Joined: 03 Apr 2018 Posts: 4

Hi all,

just seen the announcement of a new dual-core dsPIC series!
dsPIC33CH

A 90MHz main core and a 100MHz slave core, each with their own peripherals.

They look really nice for designs that need both continuous time-critical actions and slower comms like I2C that can cause timing errors in a single CPU.

http://www.microchip.com/design-centers/16-bit/products/dspic33ch

I will be looking forward to support for these in PCD.

newguy · Joined: 24 Jun 2004 Posts: 1908

I'd love to play with one too, but I cringe to think of the errata.

Ttelmah · Joined: 11 Mar 2010 Posts: 19537

Multi-core programming would require a lot beyond CCS.
C has no native support for multi-threading. There would need to be a platform under the language to support the threading, and this is going to be a lot of work.....
However this is not a multi-core processor in the normal sense, but just dual chips, in one package, with a communication/sync system (a multi-core would be sharing the resources, the description implies these don't).
Key part of description "dual independant cores'. Actually two processors with a communication FIFO, sharing the I/O pins.
There are errata already published for the chips. The UART has a lot of problems. A couple of quite nasty ones with I2C, and the same clock switching one as some of the other PIC33's. It is quite 'odd' actually. I have in the past designed processor cores, and one of the things done it to use 'library' parts. Now you still get occasional issues when the specifics of your system generate an unexpected timing, but in general once there is a working peripheral, this is used throughout the later chips, and works. MicroChip seem to design working peripherals, and then not use these on later chips, or keep using libraries that they know have issues. Strange...

temtronic · Posted: Mon Jul 16, 2018 5:13 am

This seems to be one of those 'looks great on a napkin' ideas, comes to life..and ..oopsy ! Sounds good but the reality is it'd be cheaper to just use two KNOWN PICs on the same PCB. Hate to think of the man YEARS involved in getting it to work, let alone BETTER than 2 PICs on a PCB.
Even if CCS did support it, yeesh just think of the headaches when your code doesn't work. Hmm is it PIC 'A' or PIC 'B' that is the problem ?
OK, I'm old but I'll lay odds a good code cutter can get 2 PICS to work as well as (or better) than this 2-in-1 PIC.

I'll put this in the same catagory as TPMS(Tire Pressure Monitor Sensor) technology, nice but not required.

Jay

drolleman · Joined: 03 Feb 2011 Posts: 116

I haven't ever developed an system that worked out of the gate yet. So give them a chance to get it working. I've had 4 ep processors on one board, after lengthy debugging it worked on two ep's. I regularly do multithreading (love that), I would love two processors on one chip. easier to connect, than two separate chips.

dave

rjenkinsgb · Joined: 03 Apr 2018 Posts: 4

Ttelmah · Joined: 11 Mar 2010 Posts: 19537

Er. That is exactly what I said!.....

newguy · Joined: 24 Jun 2004 Posts: 1908

temtronic · Posted: Sat Jul 21, 2018 9:44 am

Well if you think about it most of us 'old guys' are retired... PICs came out 1/2 my lifetime ago...sigh
I've never understood WHY a company 'needs' 1000+ 'variations on a theme', better to stick with a few and improve as required.

bkamen · Posted: Thu Mar 07, 2019 4:00 pm

I just noticed in the recent CCS update email.

I've been buring off in FPGA/ARM SoC land for the last several years....

Interesting indeed.

So many toys -- so little time...
_________________
Dazed and confused? I don't think so. Just "plain lost" will do. :D

temtronic · Posted: Fri Mar 08, 2019 7:03 am

I wonder if a lot of these 'new PICs' are custom ones requested by big volume customers ?
I got some samples of the 10F222 as I only needed 2in-2out, go to test and THEN discover NO timer interrupt ! Yeesh, I can't recall any PIC not having T0INT.
Oh well....

Ttelmah · Joined: 11 Mar 2010 Posts: 19537

That is actually the "raison d'etra" of 99% of PIC's.
Microchip offer a service, where if you are buying significant numbers
you basically choose the features you want, and they do a custom
chip for you. I've done it twice. As part of this you get a much lower
price if you agree to the chip being distributed afterwards. Hence most
are. It's also much cheaper if the peripherals are ones they already offer.
This is why so many PIC's have what seem to be quite 'strange'
peripheral mixes. Depending then on the 'core' you choose, some
parts come included in the core (Timers CCP etc.).

bkamen · Posted: Fri Mar 08, 2019 8:51 am

Well sure -- Microchip cranks device after device based on a given set of pluggable IP (I think I heard it was VHDL.)

They're not the only ones.

To offer that library for custom-spin parts to paying customers only makes sense.

It's as easy as making brownies. Just describe the recipe, add the ingredients, send off to the ASIC fab and wait for the timer to go off and the brownies to be delivered! Very Happy

-Ben
_________________
Dazed and confused? I don't think so. Just "plain lost" will do. :D

jeremiah · Joined: 20 Jul 2010 Posts: 1353

I'm curious how CCS would handle multicore considering the calling convention they use on functions. Since locals and function parameters are giving specific memory addresses, that prevents different cores from using the same function at the same time (or you would clobber your vars). I mean, we can always work around it with duplicate functions, but that eats up flash.

bkamen · Posted: Mon Mar 11, 2019 12:32 am