PIC24EP maximum sampling speed per input

[benoitstjean]

Device: PIC24EP512GP806
Compiler: 5.026

Hi guys,

My device is running with an internal frequency of 129.048MHz (external oscillator is 29.4912Mhz.

I don't currently have the proper setup to test at the moment but I know someone will have an answer....

Let's say I have an input with a square wave and I want to sample on every L-to-H (not by interrupt), what can be the maximum frequency that this square wave can have? 100Hz? 1MHz? 10MHz?

Thanks,

Ben

[Ttelmah]

Depends totally on what else the code is doing. No simple answer.
If it is simply sitting in a loop waiting for the edge to go high, then if using
standard I/O, you would have about 6 instruction times in the loop, so at
your 64MIPS, you could detect an edge at about 10MHz, but the speed that
things can be done, then depends on what happens when this detection
happens.

[benoitstjean]

Alrighty. For sure it would be doing way more than sampling but I guess what I wanted to try definitely won't work.

Just wanted to see if there was a way to use this with an OV2640 camera (not just the chip but the entire camera with a 24-pin FPC flat ribbon connector).

I think 10 MHz is the bit clock per frame.

Thanks!

Ben

[Ttelmah]

Problem is that in code terms, the act of writing the byte to a memory address,
and then incrementing that address takes more time.
Now some of the chips have DMA that can transfer a byte triggered by a
signal, so this might be able to read a line of data, but then you would run
out of size for the next line.
It is a key thing to understand fundamentally about the PIC, that they
always have relatively small RAM sizes. Even the DsPIC's are not suited
to handling things like video frames. You could relatively easily program
an FPGA to transfer bytes into a RAM memory on each clock, and then
have this RAM memory available on a PIC port to be worked with. However
doing something involving the whole frame would be much better suited
to a chip that can have this RAM inside it's fundamental memory map.
The Harvard architecture gains advantages by being able to fetch from
ROM and RAM at the same time, avoiding the need for the complexity of
cache RAM etc., but it has disadvantages when you want to have large
RAM areas mapped into the primary memory....