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asmboy
Joined: 20 Nov 2007 Posts: 2128 Location: albany ny
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Posted: Tue Jan 10, 2012 7:54 am |
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i have to assume that the 9600 baud options are "sampling options" - meaning that a snapshot of the absolute position data is sent at a steady 9600 baud rate. - thus at high speed - the shaft angle position words are not consecutive values .
I'm going to guess that the high speed mode was probably crafted to simply offer better time domain performance in that sphere. I think that if the shaft speed is LOW - that the 4 mb bit rate issue might not matter - as the data will not be steady at that rate - and i envision the possibility of a possible serial FIFO to make intermittant bursts of 4 MB into a more steadily accessible stream of a much lower rate.
that said, the KEY question you need to answer is: do you NEED the higher update rate - or does intermittent absolute position data work well enough? |
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asmboy
Joined: 20 Nov 2007 Posts: 2128 Location: albany ny
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Posted: Tue Jan 10, 2012 7:27 pm |
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Then there is this:
Check the IDT72142 datasheet
which you will realize is a 9 bit cascadable deserializer
meant for disk drive streams of previous generations.
See figure 14 in particular -
as there is a DANDY self clocked serial input to a PAIR of 9bit ( 18 total wide) 8192 (BYTE+1) deep - parallel 9bit x 2 wide output - with a VERY simple interface that lets it out a convenient 9 bits x2 at a time .....
( you can use a set of of HC541s or similar to share the bus outs of the two units ).
If I was going to make a serious try before heading for a much more
ambitious bit of hardware work - I'd check this part out.
Just my 2 cents worth. |
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asdf85
Joined: 03 Jan 2011 Posts: 34
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Posted: Wed Jan 11, 2012 12:20 am |
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Thanks for all the feedback |
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FvM
Joined: 27 Aug 2008 Posts: 2337 Location: Germany
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Posted: Wed Jan 11, 2012 1:10 am |
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Quote: | Check the IDT72142 datasheet
which you will realize is a 9 bit cascadable deserializer |
Implementing an UART also involves start bit detection and respective oversampling. It's more
than a simple (synchronous) deserializer.
Of course it's possible with standard logic chips, but the overall design will end up in a wire entanglement.
A recent CPLD in the 100 to 200 logic element class promises a smart single chip solution in contrast. |
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temtronic
Joined: 01 Jul 2010 Posts: 9243 Location: Greensville,Ontario
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Posted: Wed Jan 11, 2012 8:27 am |
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Yeah...in the 'good old days' you'ld grab a bunch of 7400 series dips, wire wrap them, add a good 5 volt supply and be up and running .
Now you need some fancy software to program an ittybitty micro-SMD device to do the same job.
There's lots of 'solutions' to the problem it's choosing the one that's best for the job that's the challenge ! |
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