23A1024 SRAM help

[neochrome32]

CCS: 4.130;
i haven't started the code yet, but looking to see if anyone has already done a SPI RAM project> (im wishing really to skip over this headache for time constraint)
if anyone has done this, and in QUAD mode?

link to data sheet:
http://ww1.microchip.com/downloads/en/DeviceDoc/25142A.pdf

if this isn't done before, i'll do the best i can to make one working and post the code

[bkamen]

before diving in:

Ask yourself this question:

1: What would be the benefit of the QSPI mode?
2: How would you implement that in hardware for the best performance gains? (answer: you wouldn't. There is no QSPI module on any PIC I've seen yet.)
3: Now that you know you'd have to do the QSPI in software, would the speed of QSPI still exist at software bit-banged speeds? (no)
4: Rewind back to #1.



Honestly, if you stick with regular SPI, you'll get hardware modules doing the job as fast as it can be done PLUS there's a lot of pre-written drivers in CCS's included library with the compiler.
_________________
Dazed and confused? I don't think so. Just "plain lost" will do. :D

[neochrome32]

Thats what i thought too...

im planning on using the 46k22 which has a bit of speed behind it, but been looking over the datasheets, i wont know yet as the MCU is still using software SPI; the hardware is used on the SDCARD side, with only SDI mode, i dont mind the lack of speed but having 4bit would still improve stuff.

think im just gonna have to build a prototype to test with i think

[edit]
i couldn't find the pre-written stuff for spi/sqi mode for this SRAM! lol

[Ttelmah]

Thing is that generally, the limitation is how fast the PIC can move data, not the speed of SPI. Even using table read instructions, just loading a byte, transferring it to the SPI register, looping & counting, takes more time than the single bit SPI takes to transfer the byte at the maximum clock rate....

Best Wishes

[neochrome32]

i have a total grasp of cycles needed to do each instruction, I'm aware of the limitations and i know i cant hope to reach the 100% speed capacity,

just needed to know if there was ready made code for 4bit sram, read..

to be honest its looking like,

converting 4nibbles to 1byte is gonna take about the same amount of cycles as just shifting bits into a 8bit buffer! lol

i still cant find any source code for the 23A1024 (1mbit) = 128kByte (just like my spectrum +2

[PCM programmer]

CCS has a driver for a smaller SRAM (32KB instead of 128KB) here:

[neochrome32]

-_- are you kidding me! i cant believe i missed that!!
sorry!!

[neochrome32]

And Thank you

[ckielstra]

[neochrome32]

24LC1024 - is EEPROM

23A1024 is SRAM (which i need) so part is correct, i dont need ROM tho

[Ttelmah]

It is the overlapping of the I/O available with the hardware SPI, that is the critical point. Assuming that you actually will have something like a data counter, the time taken to do this, takes the minimum 6 cycles needed to send a byte by sending a nibble, clocking this, then using the swap instruction to get the other nibble, and clock this, to more than 8 cycles. By which time the hardware SPI has already sent the data.
The interface format between the 23LC1024, and the 24LC1024, is designed to be basically the same. One is EEPROM, the other SRAM. Difference is that you don't have to wait for the write on the SRAM, but the actual interfacing (in SPI mode) is identical.
As Ckielstra says, the key for performance is to use the hardware SPI, and bypass the CCS functions (I have always felt it is a pity they don't have a settable flag, or an extra parameter like the read_adc function - so you could specify to return immediately).
The real pity is that a memory like this is ideal for use with addressmod, to give a fast large RAM data space. However compilers with working addressmod versions seem to be getting rarer and rarer...

Best Wishes