Interesting Problem !

[ezflyr]

Hi,

Your layout is much better, but it's still not ideal. The problems I see are:

1. The connections to the 'plane' layers are really anemic. Your software is using a very small width etch to connect a Vcc or Gnd pin to the associated plane. Generally, the connection is made with some 'thermal relief', ie. it's not a total connection, but in your case this setting is too aggressive.

2. I don't see any filtering or bypass capacitors near to the power input connector. You don't want to omit these.

John

PS Why did you stop responding to your 'other' thread?

[musti463]

Ok thank you. I will apply your tips on my layout. Am i pass ground and power plane under the oscillator circuit? And should i add inductor between RS485 transreceiver's and PIC's power/ground pins?


PS I am using this layout for my RS485 communication tryings. And i want to be sure about my hardware and look totally my software.
_________________
M.Emir SADE

[newguy]

Be careful with power or ground planes and their proximity to crystals/crystal traces/crystal capacitors. The oscillator has tight tolerances on capacitance and a co-planar plane (to the oscillator traces) can add significant capacitance - enough that the oscillator won't start up. Put a "keep out" polygon over your oscillator and oscillator traces, do the power/ground (whatever is on the same plane as the oscillator traces) pour, then remove the keep out poly and then pour the other side.



This is the 32.768 kHz crystal (Y1) for a MCP79412 real time clock on a board we have in production. Notice that the pour isn't close to it but it's okay for it to be close to the ground pads of the oscillator's capacitors.

[Ttelmah]

Also, look at the thickness of newguy's traces. The traces to each of your I/O ports are many times thicker than they want to be. This gains you nothing, and may actually cause problems. As it stands it results in enormous holes in the power planes.
Then one 'old trick' is to tend to use a particular direction on the top of the board, and the opposite on the bottom. So traces running 'across' are on the top, while those running 'up' are on the bottom for example.

[musti463]

I changed again.What do you think now? I wanna get OK from you about my layout

Top Layer


Bottom Layer

_________________
M.Emir SADE

[temtronic]

some of 'points' come to mind.....

1) you should replace 'J9' so that it's + is on the left side, the same as J8 and J10. Since none of the headers are 'keyed' you could(will !)put the cable on J9 wrong at least once thinking it's the same polarity as the others. You have the choice now to make them the same.

2) if you replace the RS485 device 90* you'll get a better placement of parts and wiring, and it's pin 1 is similar to the PICs pin 1

3)you can get rid of the jumper for R1 if you replace that component.

4)you should add the 'option' of a pullup resistor pack on the I/O ports.

5) you could use straight lines from the PIC to the I/O headers.

6) C3 could be moved,again making the layout 'neater'.

7) signal traces should be thicker,less chance they'll disconnect when resoldering components.

8) allow space for IC sockets ! You've got lots of room, sockets are cheap and allow for EASY replacement of PIC and other devices.

9) I'd move the contrast pot further from the PIC, seems 'close' to me.

10) add four big round pads in the corners as 'mounting holes'.ensure NO copper touches them( Vdd or ground)

11) add additional pads for extra filter and bypass caps as well as flywire points for Vdd and ground.

12) J1 ( RS485) might be better as +ABG instead of +GAB

13) add a 'grid' of unconnected free pads for additonal parts.

14) size of board.Find a box you like(bigger of course) and make the PCB fit it.This will dictate mtg holes, I/O orientation,etc. but it's a LOT easier designing the PCB to fit the box than trying to find a box that will fit the PCB.

When laying out PCBs I've always grabbed the components, placed on perfboard and 'played' PCB router before either solder stitching or letting a computer program do the artwork. Things always fit on the screen BUT in the real world they are tighter, harder to work on. If you don't hve the real chips, use IC sockets as the parts. After 25+ years I still prefer to do it this way...I don't trust ANY PCB layout programs to 'adjust' for my fat fingers while soldering parts. Smaller boards are NOT better!

hth
jay

[Ttelmah]

He is a bit 'heavy handed'. Moved from using perhaps 1mm tracks to perhaps 0.2mm. 0.3mm is a standard track that it thick enough, and yet not 'OTT'.

He is still low on decoupling. One across the pot. One by each power connector. A diode to short out the power if it is connected backwards.

Generally he should be making more use of the top of the board, to give less holes in the ground plane.

[newguy]

Spacing between your bottom layer plane (assume it's ground) and your crystal traces is too small.

[musti463]

[Ttelmah]

He means increase the gap between the traces and the plane in this area.

[PCM programmer]

[musti463]

I changed like this (i tied caps to ground)


_________________
M.Emir SADE

[ezflyr]

Hi,

Er....... No....... Your crystal loading capacitors are no longer connected to ground.....

Don't you have anyone local that knows anything about PCB design? Frankly, PCB design "by forum" is really inefficient, and is probably not teaching you a whole lot.....

John

[Tom Jetland]

My old boss told me to never have IO pins going straight to connectors; always series with a protection resistor to prevent ESD problems etc.

Also, he never trusted tantalum caps as he knew about their tendency to go POP! Maybe that's not the case now but it was 20 years ago. Anyway, what with high value SMD X7R caps being a plenty now, it's not so much of an issue.

Tom

[Ttelmah]

Tantalum capacitors can be a problem.
You can get 'military certified' types, that are now legal in military, and medical applications, where conventional tantalum's are not, because of their failure modes. Look for 'high reliability' certifications. Problem of course, is that these are more expensive, than the alternative, of perhaps a conventional low ESR aluminium capacitor, in parallel with a ceramic capacitor.....
I do still cringe, if I see a conventional tantalum, in a circuit, where failure would be catastrophic. They are a technology, that needs to be used with care.