PLL configuration question [SOLVED]

[benoitstjean]

Compiler: 5.026
Device: PIC24EP512GP806

The MCU is tied to an external 36.864MHz crystal (not a powered oscillator).

I have the fuses set like this:

#fuses HS, PR, NOWDT, WINDIS, WPOSTS16, NOJTAG, NODEBUG, NOIESO

And the oscillator configuration set like this:

#use delay( crystal = 36864000, clock = 73728000 )


I know there's much more to these two commands for setting-up the PLL but I take for granted that this is all done internally by the compiler.

But how would I go about to take advantage of the two lines above to use the maximum speed out of the PLL?

I realize that the current draw will be higher but I just want to get this thing to run as fast as I can for other reasons.

Microchip's document DS70580C-page 7-26 states that with PLL, 120 MHz < FSYS < 340 MHz.

Does this mean that I could change the <clock = 73728000> (73.728MHz) to <clock = 331776000> (331.776MHz -> 9x the initial xtal speed and less than 340MHz)?

Thanks again,

Benoit

[temtronic]

Without looking at the chip's datasheet, I'd say *8 not *9 as 9 ain't a good 'binary' number.
I'm probably wrong but check the 'clock config' section of the PIC. I prefer to look at the 'clock flowchart' picture. It'll have the dividers listed on it, possible clock data paths, etc.

jay

[Ttelmah]

No.

Fsys, is not the clock frequency.

The maximum clock frequency supported is 140MHz (below 85C).

Now the oscillators on all the DSPIC's, when using he PLL get quite complex.
The crystal is fed in and is divided by PLLPRE to give a frequency between 0.8Mhz and 8MHz. This then feeds the PLL, and is multiplied by PLLDIV. The output of this must be between 120, and 340MHz. This then feeds the postscaler and is divided down. The result is Fosc, which must be below 120Mhz (for the full temperature range), or 140Mhz (for the reduced 85C range). Now several of these multiplications and divisions have restricted values. So PLLPOST only supports /2, /4, & /8. PLLPRE, supports /2 to /33, & PLLDIV supports 2 to 513.

Now as a comment, you can see that your crystal will be divided massively before being fed to the PLL. It actually wastes a little power, and increases RF radiation to use a faster crystal than is needed. Assuming you have some reason to be using the particular 36.864MHz multiple, you'd be better off choosing perhaps a 7.3728MHz crystal. Otherwise simply use 8MHz.

Now you always get the most accurate final value, by using the largest multiplier on the PLL. However 340Mhz does not give us the maximum Fosc frequency. Fosc MAX is 140Mhz. Since PLLPOST only supports /2, /4 & /8, the best frequency we can use is Fvco=280MHz.

280MHz/36.864 = 7.5954

Now we need a total divider just slightly _larger_ than this. So lets look for multiples of this between *2 and *33, that are just _above_ an integer. *22, gives 167.1. So if we divide the incoming signal by 22, to give 1.675636Mhz, and then multiply by 167, we get 279.8Mhz. With a postscale of /2. This then gives an Fosc of 139.7Mhz, Within a tiny fraction of a percent of the maximum possible.

So if you setup your oscillator with:

#use delay( crystal = 36.864MHz, clock = 139.672Mhz )

You'll be running as fast as possible with this crystal.

[benoitstjean]

Hi Ttelmah,

Always interesting to read your responses! Thanks!

I use a 36.864MHz crystal because of several other timing signals I have on my circuit.

First thing is the UART, I wanted to have a crystal that would provide, based on theoretical calculations, 0% error for the UART speeds. I know there's always a slight margin of error because of frequency drift and other factors but at least the theoretical calculation gives 0% vs, let's say, 35MHz which would probably have errors when calculating (note here I chose 35MHz randomly).

Also, with that specific frequency, it gives me the ability to generate a 128kHz 50% duty PWM, a 2.4576MHz 50% duty PWM and a 3.072 50% duty PWM for external devices. These frequencies need to be very precise for the external devices they are feeding.

I could use also 29.4912 MHz, or 24.576MHz etc, as longs as I can generate the correct PWM's and UART speed and run as fast as I can with the PLL. I will go over your calculations this morning to try to understand it alongside the Oscillator datasheet from Microchip.

I think I will make myself an Excel spreadsheet where you plug-in a crystal speed and if does all the calculations for you for the PLL. As a side note, if anyone reading this is interested, I have such spreadsheet for the PWM and UART calculations and makes it easy to calculate (although it's not super complex)... you can plug-in the PWM speed you want and it changes the crystal speed based on other PWM settings. Or plug-in the crystal speed and change the settings and it shows you the PWM speed you will get. Just message me in the private messages.

Anyhow, thanks for all the details both you and Temtronic, I will try this morning with the 139.672MHz clock using my crystal. I might have to crank-it down a bit below 120MHz because here in Canada, I need this thing to run as low as -40C to be within spec.

Benoit

[newguy]

[Ttelmah]

For Benoit, it is not normally low temperatures that cause problems for semiconductors (does for capacitors and some other parts though...).

[benoitstjean]

Hi again TTelmah,

I'm trying to make sense of your calculations while I'm following page 7-23 in document DS70580C from Microchip. I'm making the calculations in an Excel spreadsheet and my numbers don't match all your calculations:

Here are the numbers and calculations I have and correct me if I'm wrong:

Fin: 36,864,000 Hz
N1: 20
M: 165
N2: 1

I took the Fplli calculation from page 7-24 Equation 7-5:
Fplli = Fin * (1/N1) = 36,864,000 * (1/20) = 1,843,200 Hz (not 1,675,636.36MHz like your calculation)

I took the Fsys calculation from page 7-23 Equation 7-3:
Fsys = Fin * ((M + 2)/(N1 + 2)) = 36,864,000 * ((165 + 2) / (20 + 2)) = 279,831,272.73MHz (like you indicated)

But here is where my calculation is totally not the same as yours for Fosc. I took the Fosc calculation from page 7-23 Equation 7-4:

Fosc = Fin * ((M+2) / ((N1 + 2) * (2*( N2 + 1))) = 36,864,000 * ((165+2) / ((20+2) * (2*(1+1))) = 67,957,818.18MHz (totally not what you calculated at 139.672MHz)

So where is the error? How did you get to 139.672MHz?

I will re-look at the calculations again.

Thanks,

Benoit

[Ttelmah]

N2=0, gives /2

2*(0+1) not 0+1.

So double the frequency out.

[benoitstjean]

Ah! I think I see what you mean now... Is it possible you made a calculation error somewhere?

Here are my calculations:

Fplli = Fin x (1 / (value of N1+2)) = 36,864,000 x (1 / (20 + 2)) --> Divided by 22 = 1,675,636.36 MHz --> Same as you


Fsys = Fin x ((value of M + 2)/(value of N1 + 2)) = 36,864,000 x ((165 + 2) / (20 + 2)) = 279,831,272.73 MHz --> Same as you

Fosc = Fin x ((value of M+2) / ((value of N1 + 2) x (2x(value of N2 + 1))) = 36,864,000 x ((165+2) / ((20+2) x (2x(0+1))) = 36,864,000 x (167 / 44) = 139,915,636.36MHz --> Not same as you (139.672Mhz)

Thanks again,

Benoit

[Ttelmah]

Problem is we are always trying to 'second guess' what the compiler does....

I got the same figure as you, using the 'absolute best' calculation I showed.

However the compiler actually sets it slightly differently, and gives 139.672. If you try to select 139.915, you will find you get 139.672.

Now it is nice to not have to worry about the calculation, and the compiler seems to make a pretty good job of it. However it would be really nice to be able to specify the divisions yourself, for a situation like this.

[benoitstjean]

Ah ok.

So now, based on my calculations, I will use the following values:

N1 = 20
M = 163
N2 = 0

This will give me an Fosc of 138,240,000MHz sharp therefore my PWM calculations will provide me with the correct outputs required of 128kHz and 2.7648MHz _and_ an exact 115200 BPS speeds with 0% calculation error.

The two PWM's feed into an external part which also uses a PLL to generate other signals.

Thanks a million,

Benoit

[benoitstjean]

Hello again,

As stated earlier, I need the PLL clock to be a precise frequency just because this frequency is required for the following features:

1) 0% error calculation for UART speeds of 115200 bps and 230400 bps;
2) 128kHz PWM;
3) Another PWM between 2 and 3.5MHz;

So for the excercise, I made a nice big Excel spreadsheet where I can plug-in different PLLPRE/PLLDIV/PLLPOST values and all the calculations are done, including the UART baud rate calculations and PWM frequency.

Then I look at the PLL values I put-in and eliminate the lines that do not respect the ranges for any given PLL parameter but I also eliminate the ones that calculate wrong UART speeds and PWM frequencies.

This cuts-down drastically on the possibilities, especially given that the PLLPRE is only from 2-33.

So after doing the calculations and staying within specs for all variables, there's one possibility for every PLLPRE from 2-33 and PLLDIV from 33 to 243 by steps of 7.

And it turns-out that the only Fosc end-result calculation that is good for all my requirements is 129.024MHz.

Here are some calculations result (these are columns and rows so make your screen big):

Fin PLLPRE Fplli PLLDIV Fsys PLL POST Fosc
36,864,000.00 3 7,372,800.000000 33 258,048,000.00 0 129,024,000.00
36,864,000.00 4 6,144,000.000000 40 258,048,000.00 0 129,024,000.00
36,864,000.00 5 5,266,285.714286 47 258,048,000.00 0 129,024,000.00
36,864,000.00 6 4,608,000.000000 54 258,048,000.00 0 129,024,000.00
36,864,000.00 7 4,096,000.000000 61 258,048,000.00 0 129,024,000.00
36,864,000.00 8 3,686,400.000000 68 258,048,000.00 0 129,024,000.00
36,864,000.00 9 3,351,272.727273 75 258,048,000.00 0 129,024,000.00
36,864,000.00 10 3,072,000.000000 82 258,048,000.00 0 129,024,000.00
36,864,000.00 11 2,835,692.307692 89 258,048,000.00 0 129,024,000.00
36,864,000.00 12 2,633,142.857143 96 258,048,000.00 0 129,024,000.00
36,864,000.00 13 2,457,600.000000 103 258,048,000.00 0 129,024,000.00
36,864,000.00 14 2,304,000.000000 110 258,048,000.00 0 129,024,000.00
36,864,000.00 15 2,168,470.588235 117 258,048,000.00 0 129,024,000.00
36,864,000.00 16 2,048,000.000000 124 258,048,000.00 0 129,024,000.00
36,864,000.00 17 1,940,210.526316 131 258,048,000.00 0 129,024,000.00
36,864,000.00 18 1,843,200.000000 138 258,048,000.00 0 129,024,000.00
36,864,000.00 19 1,755,428.571429 145 258,048,000.00 0 129,024,000.00
[color=red]36,864,000.00 20 1,675,636.363636 152 258,048,000.00 0 129,024,000.00
[color=red]36,864,000.00 21 1,602,782.608696 159 258,048,000.00 0 129,024,000.00
[/color]36,864,000.00 22 1,536,000.000000 166 258,048,000.00 0 129,024,000.00
[...] and so on [...]
36,864,000.00 33 1,053,257.142857 243 258,048,000.00 0 129,024,000.00


This being said, what's the rule here? Is there a combination above that is better than the other? Or should I go by as long as all values are within specs, it's good?

The only other thing I can think of, which I doubt will change anything, is that in the above list, although the end Fosc is always 129.024MHz and Fsys is always 258.048MHz, some of them yield an Fplli that is not on a perfect boundary and I have highlighted them in red in the list.

So which is best to choose? Personally I would think that a perfect frequency is always better but I'm no expert in this area.

Thanks again,

Ben

[temtronic]

ben

My 'gut' is telling me to NOT use those red coloured options. Odd ball numbers just don't sit well with me.

I have zero knowledge about that PIC, but IF there's any peripheral ( future 'must have'....) that needs Fplli (again, I don't know if that's available) perhaps consider a divider that gives a 'nice' number...something that again ends in a lot of zeros....
2.457600 is 'nice' to me.

There is no 'perfect' choice, just a 'best' one based on your current requirements. That will change 2 days from now when '''oh yeah...now I NEED....."

Jay

[benoitstjean]

heheh, yes, I like perfect round numbers as well.

Let's see what TTelmah has to say if he answers!

He will most likely have (again) a logical explanation to all of these mumbo-jumbo PLL calculations.

Perhaps the lowest Plli possible would help in reducing noise maybe? The smallest Fplli value to give a nice frequency with all 0's is PLLPRE of 30 and PLLDIV of 222.

But quite frankly, now that I think of it, I am not even choosing those values myself, I just plug-in the PLL frequency I want and CCS does the magic in the background assuming _they_ use the golden rules to get the best parameters.

Thanks,

Ben

[Ttelmah]

Sorry to have been quiet. 500mile drive to go and pick up some bits I had bought at auction, so computer was 'off'...

Now it is very interesting to just try the expedient of compiling: