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SPI1 doesn't work in PIC18F47J13-TQFP.
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Josep Robert



Joined: 27 Mar 2018
Posts: 25

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SPI1 doesn't work in PIC18F47J13-TQFP.
PostPosted: Tue Mar 27, 2018 10:44 am     Reply with quote

Problem Description:

I’m using PIC18F47J13-TQFP.

Working with SPI I realized the following:

Using SPI1 with default pins it doesn’t work but using SPI2 and remapping pins to match the default pins (to maintain the hardware) then it works correctly.

SPI1 code, it doesn't works:

Code:

CCS PCH C Compiler, Version 5.076             26-mar.-18 09:19

               Filename:   C:\Users\jrobert\MPLABXProjects\PIC18F47J13_SPI.X\build\default\production\PIC18F47J13_SPI1_KO.lst

               ROM used:   76 bytes (0%)
                           Largest free fragment is 65528
               RAM used:   4 (0%) at main() level
                           4 (0%) worst case
               Stack used: 0 locations
               Stack size: 31

*
00000:  GOTO   0004
.................... #include <18F47J13.h>         // PIC18F47J13-TQFP 44 pins
.................... //////////// Standard Header file for the PIC18F47J13 device ////////////////
.................... ///////////////////////////////////////////////////////////////////////////
.................... ////        (C) Copyright 1996, 2014 Custom Computer Services          ////
.................... //// This source code may only be used by licensed users of the CCS C  ////
.................... //// compiler.  This source code may only be distributed to other      ////
.................... //// licensed users of the CCS C compiler.  No other use, reproduction ////
.................... //// or distribution is permitted without written permission.          ////
.................... //// Derivative programs created using this software in object code    ////
.................... //// form are not restricted in any way.                               ////
.................... ///////////////////////////////////////////////////////////////////////////
.................... #device PIC18F47J13
.................... 
.................... #list
.................... 
.................... 
.................... #CASE                         // Case sensetive compiler
.................... 
.................... #device adc = 10
.................... 
.................... // Configuration Bits:
.................... 
.................... #FUSES ADC10                                       // ADC is 10/12-bits
.................... 
.................... #FUSES NOWDT                                       // No Watch Dog Timer
.................... #FUSES WDT128                                      // Watch Dog Timer uses 1:128 Postscale
.................... #FUSES STVREN                                      // Stack full/underflow will not cause reset
.................... #FUSES NOXINST                                     // Extended set extension and Indexed Addressing mode disabled (Legacy mode)
.................... #FUSES INTRC_IO                                    //Internal RC Osc, no CLKOUT
.................... #FUSES NOCLOCKOUT           
.................... #FUSES NOFCMEN                                     // Fail-safe clock monitor disabled
.................... #FUSES NOIESO                                      // Internal External Switch Over mode disabled
.................... #FUSES RTCOSC_INT                                  // RTCC uses Internal 31KHz Oscillator as reference source
.................... #FUSES NODSBOR                                     // BOR disabled in Deep Sleep
.................... #FUSES NODSWDT                                     // Deep Sleep Watchdog Timer disabled
.................... #FUSES NOWPFP                                      // Write/Erase Protect Page
.................... 
.................... #FUSES SOSC_LOW                                    // Per defecte el CCS posa "#FUSES SOSC_DIG Digital mode, I/O port functionality of RC0 and RC1"
.................... 
.................... #use delay(clock = 16MHZ, internal)
.................... 
.................... // PIN_C4     // SPI1 Data Input     Pin 42
.................... // PIN_C5     // SPI1 Data Output    Pin 43
.................... // PIN_C3     // SPI1 Clock Output   Pin 37   4MHz
.................... 
.................... void main(void)
00004:  CLRF   FF8
00006:  BCF    FD0.7
00008:  MOVLW  60
0000A:  MOVWF  FD3
0000C:  CLRF   F9B
0000E:  CLRF   F64
00010:  MOVLW  FF
00012:  MOVLB  F
00014:  MOVWF  x48
00016:  BCF    FC2.6
00018:  BCF    FC2.7
0001A:  MOVF   x49,W
0001C:  ANDLW  E0
0001E:  IORLW  1F
00020:  MOVWF  x49
00022:  CLRF   x25
00024:  CLRF   FD1
00026:  CLRF   FD2
.................... {
....................    setup_spi (SPI_MASTER | SPI_L_TO_H | SPI_XMIT_L_TO_H);
00028:  BCF    FC6.5    // SSP1CON1.SSPEN = 0 = Disables serial port and configures these pins as I/O port pins
0002A:  BCF    F94.5    // TRISC.5 = 0 = PIN_C5 output
0002C:  BSF    F94.4    // TRISC.4 = 1 = PIN_C4 input
0002E:  BCF    F94.3    // TRISC.3 = 0 = PIN_C3 output
00030:  MOVLW  20
00032:  MOVWF  FC6      // SSP1CON1 = 0x20 => bit5 = 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
00034:  MOVLW  40
00036:  MOVWF  FC7      // SSP1STAT = 0x40 => bit7 = 0 = Input data sampled at the middle of data output time
                        //                    bit6 = 1 = Transmit occurs on transition from active to Idle clock state
....................     
....................    while(1)
....................    { 
....................       spi_write(0x55);
00038:  MOVF   FC9,W    // SSP1BUF
0003A:  MOVLW  55
0003C:  MOVWF  FC9      // SSP1BUF
0003E:  RRCF   FC7,W    // SSP1STAT bit 0 Buffer full status bit = 0 = Receive not complete, SSPxBUF is empty
00040:  BTFSS  FD8.0    // STATUS.CARRY
00042:  GOTO   003E
00046:  GOTO   0038
....................    }
.................... }
*
0004A:  SLEEP

Configuration Fuses:
   Word  1: F4AC   NOWDT PLL2 PLLEN STVREN NOXINST NODEBUG NOPROTECT
   Word  2: F70A   INTRC_PLL_IO SOSC_LOW NOCLOCKOUT NOFCMEN NOIESO WDT128
   Word  3: FFF1   DSWDTOSC_INT RTCOSC_INT NODSBOR NODSWDT IOL1WAY ADC10 PLL MSSPMSK7
   Word  4: F380   NOWPFP NOWPCFG WPDIS WPEND


SPI2 code, it works:

Code:

CCS PCH C Compiler, Version 5.076, 40786               26-mar.-18 09:47

               Filename:   C:\Users\jrobert\MPLABXProjects\PIC18F47J13_SPI.X\build\default\production\PIC18F47J13_SPI2_OK.lst

               ROM used:   126 bytes (0%)
                           Largest free fragment is 65528
               RAM used:   4 (0%) at main() level
                           5 (0%) worst case
               Stack used: 0 locations
               Stack size: 31

*
00000:  GOTO   0004
.................... #include <18F47J13.h>         // PIC18F47J13-TQFP 44 pins
.................... //////////// Standard Header file for the PIC18F47J13 device ////////////////
.................... ///////////////////////////////////////////////////////////////////////////
.................... ////        (C) Copyright 1996, 2014 Custom Computer Services          ////
.................... //// This source code may only be used by licensed users of the CCS C  ////
.................... //// compiler.  This source code may only be distributed to other      ////
.................... //// licensed users of the CCS C compiler.  No other use, reproduction ////
.................... //// or distribution is permitted without written permission.          ////
.................... //// Derivative programs created using this software in object code    ////
.................... //// form are not restricted in any way.                               ////
.................... ///////////////////////////////////////////////////////////////////////////
.................... #device PIC18F47J13
.................... 
.................... #list
.................... 
.................... 
.................... #CASE                         // Case sensetive compiler
.................... 
.................... #device adc = 10
.................... 
.................... // Configuration Bits:
.................... 
.................... #FUSES ADC10                                       // ADC is 10/12-bits
.................... 
.................... #FUSES NOWDT                                       // No Watch Dog Timer
.................... #FUSES WDT128                                      // Watch Dog Timer uses 1:128 Postscale
.................... #FUSES STVREN                                      // Stack full/underflow will not cause reset
.................... #FUSES NOXINST                                     // Extended set extension and Indexed Addressing mode disabled (Legacy mode)
.................... #FUSES INTRC_IO                                    //Internal RC Osc, no CLKOUT
.................... #FUSES NOCLOCKOUT           
.................... #FUSES NOFCMEN                                     // Fail-safe clock monitor disabled
.................... #FUSES NOIESO                                      // Internal External Switch Over mode disabled
.................... #FUSES RTCOSC_INT                                  // RTCC uses Internal 31KHz Oscillator as reference source
.................... #FUSES NODSBOR                                     // BOR disabled in Deep Sleep
.................... #FUSES NODSWDT                                     // Deep Sleep Watchdog Timer disabled
.................... #FUSES NOWPFP                                      // Write/Erase Protect Page
.................... 
.................... #FUSES SOSC_LOW                                    // Per defecte el CCS posa "#FUSES SOSC_DIG Digital mode, I/O port functionality of RC0 and RC1"
.................... 
.................... #use delay(clock = 16MHZ, internal)
.................... 
.................... #pin_select SDI2    = PIN_C4     // SPI2 Data Input      Pin 42
.................... #pin_select SDO2    = PIN_C5     // SPI2 Data Output     Pin 43
.................... #pin_select SCK2OUT = PIN_C3     // SPIC2 Clock Output   Pin 37   4MHz
.................... 
.................... #use spi (SPI2, MASTER, MODE=0, BITS=8, baud=115200)
.................... 
.................... void main(void)
00004:  CLRF   FF8
00006:  BCF    FD0.7
00008:  MOVLB  E
0000A:  MOVLW  55
0000C:  MOVWF  FA7
0000E:  MOVLW  AA
00010:  MOVWF  FA7
00012:  BCF    xBF.0
00014:  MOVLW  0F
00016:  MOVWF  xFC
00018:  MOVLW  0B
0001A:  MOVWF  xCE
0001C:  MOVLW  0A
0001E:  MOVWF  xD0
00020:  MOVLW  55
00022:  MOVWF  FA7
00024:  MOVLW  AA
00026:  MOVWF  FA7
00028:  BSF    xBF.0
0002A:  MOVLW  60
0002C:  MOVWF  FD3
0002E:  CLRF   F9B
00030:  CLRF   F64
00032:  BCF    F72.5
00034:  MOVLW  40
00036:  MOVWF  F73
00038:  MOVLW  22
0003A:  MOVWF  F72
0003C:  BCF    F94.5
0003E:  BSF    F94.4
00040:  BCF    F94.3
00042:  MOVLW  FF
00044:  MOVLB  F
00046:  MOVWF  x48
00048:  BCF    FC2.6
0004A:  BCF    FC2.7
0004C:  MOVF   x49,W
0004E:  ANDLW  E0
00050:  IORLW  1F
00052:  MOVWF  x49
00054:  CLRF   x25
00056:  CLRF   FD1
00058:  CLRF   FD2
.................... {
....................    setup_spi2 (SPI_MASTER | SPI_L_TO_H | SPI_XMIT_L_TO_H);
0005A:  BCF    F72.5    // SSP2CON1
0005C:  BCF    F94.5
0005E:  BSF    F94.4
00060:  BCF    F94.3
00062:  MOVLW  20
00064:  MOVWF  F72    // SSP2CON1
00066:  MOVLW  40
00068:  MOVWF  F73    // SSP2STAT
....................     
....................    while(1)
....................    { 
....................       spi_write2(0x55);
0006A:  MOVF   F75,W    // SSP2BUF
0006C:  MOVLW  55
0006E:  MOVWF  F75      // SSP2BUF
00070:  RRCF   F73,W    // SSP2STAT
00072:  BTFSS  FD8.0
00074:  GOTO   0070
00078:  GOTO   006A
....................    }
.................... }
*
0007C:  SLEEP

Configuration Fuses:
   Word  1: F4AC   NOWDT PLL2 PLLEN STVREN NOXINST NODEBUG NOPROTECT
   Word  2: F70A   INTRC_PLL_IO SOSC_LOW NOCLOCKOUT NOFCMEN NOIESO WDT128
   Word  3: FFF1   DSWDTOSC_INT RTCOSC_INT NODSBOR NODSWDT IOL1WAY ADC10 PLL MSSPMSK7
   Word  4: F380   NOWPFP NOWPCFG WPDIS WPEND


Is there any issue about SPI1 with this part?

Pictures from my oscilloscope in both cases: https://imgur.com/a/CirBx

Thank you very much.

Best Regards,
Josep Robert


Last edited by Josep Robert on Wed Mar 28, 2018 10:44 am; edited 1 time in total
Ttelmah



Joined: 11 Mar 2010
Posts: 19552

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PostPosted: Tue Mar 27, 2018 11:37 am     Reply with quote

Not that I know of.

You should either use #use, or setup. Not both. With #use, uses spi_xfer, not spi_read/write. They are two different not compatible sets of code. Look at the manual. setup makes no reference to #use. #use only uses spi_xfer.
You shouldn't mix these two setups.
Use #use and spi_xfer. This is the more flexible set of code.
I've used both ports on the surface mount version of this chip without problems. I used #use only.
Ttelmah



Joined: 11 Mar 2010
Posts: 19552

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PostPosted: Wed Mar 28, 2018 1:42 am     Reply with quote

Just went and had a look at my code.
What happens if you select a lower bit rate?.
Code:

#include <18F47J13.h>
#device ADC=10
#FUSES ADC10                                       // ADC is 10/12-bits
#FUSES NOWDT                                       // No Watch Dog Timer
#FUSES STVREN                                      // Stack full/underflow will cause reset
#FUSES NOXINST                                     // Extended set extension and Indexed Addressing mode disabled (Legacy mode)
#FUSES INTRC_IO                                    //Internal RC Osc, no CLKOUT
#FUSES NOCLOCKOUT           
#FUSES NOFCMEN                                     // Fail-safe clock monitor disabled
#FUSES NOIESO                                      // Internal External Switch Over mode disabled
#FUSES RTCOSC_INT                                  // RTCC uses Internal 31KHz Oscillator as reference source
#FUSES NODSBOR                                     // BOR disabled in Deep Sleep
#FUSES NODSWDT                                     // Deep Sleep Watchdog Timer disabled
#FUSES NOWPFP                                      // Write/Erase Protect Page
#FUSES SOSC_LOW                                    // Per defecte el CCS posa

#use delay(clock = 16MHZ, internal)

#USE SPI(SPI1 MODE=0, STREAM=SPI_TEST, BITS=8, BAUD=400000)

void main(void)
{
    delay_ms(100);
    while(TRUE)
    {
        spi_xfer(SPI_TEST,0x55);
    }
}

There is an erratum on another similar chip, where the fastest divisor won't work in master mode on SPI1. Isn't listed as applying to this one, but it is possible it has the same problem.

I'm running SPI1 across an opto-coupler to a piggyback board, so am limited in baud rate
Josep Robert



Joined: 27 Mar 2018
Posts: 25

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PostPosted: Wed Mar 28, 2018 10:35 am     Reply with quote

I've just compiled your code, adding a comma,
#USE SPI(SPI1, MODE=0, STREAM=SPI_TEST, BITS=8, BAUD=400000)
and the problem is the same I posted, look at the oscilloscope:
https://imgur.com/a/CzMk4

---------------------------------------------------------------------------------

Same problem with the following code using SPI2:
Code:

#include <18F47J13.h>
#device ADC=10
#FUSES ADC10                                       // ADC is 10/12-bits
#FUSES NOWDT                                       // No Watch Dog Timer
#FUSES STVREN                                      // Stack full/underflow will cause reset
#FUSES NOXINST                                     // Extended set extension and Indexed Addressing mode disabled (Legacy mode)
#FUSES INTRC_IO                                    //Internal RC Osc, no CLKOUT
#FUSES NOCLOCKOUT           
#FUSES NOFCMEN                                     // Fail-safe clock monitor disabled
#FUSES NOIESO                                      // Internal External Switch Over mode disabled
#FUSES RTCOSC_INT                                  // RTCC uses Internal 31KHz Oscillator as reference source
#FUSES NODSBOR                                     // BOR disabled in Deep Sleep
#FUSES NODSWDT                                     // Deep Sleep Watchdog Timer disabled
#FUSES NOWPFP                                      // Write/Erase Protect Page
#FUSES SOSC_LOW                                    // Per defecte el CCS posa

#use delay(clock = 16MHZ, internal)

#USE SPI(SPI2, MODE=0, di=PIN_C4, do=PIN_C5, clk=PIN_C3, stream=SPI_TEST, BITS=8, BAUD=400000)

#pin_select SDI2    = PIN_C4  // SPI2 Data Input      Pin 42
#pin_select SDO2    = PIN_C5  // SPI2 Data Output     Pin 43
#pin_select SCK2OUT = PIN_C3  // SPIC2 Clock Output   Pin 37

void main(void)
{
    delay_ms(100);
    while(TRUE)
    {
        spi_xfer(SPI_TEST,0x55)
    }
}


(Look at the beginning, pictures added:
Pictures from my oscilloscope in both cases: https://imgur.com/a/CirBx).
PCM programmer



Joined: 06 Sep 2003
Posts: 21708

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PostPosted: Wed Mar 28, 2018 8:24 pm     Reply with quote

One problem is that you are not doing things in the correct order.
The compiler has to know what pins to use before it sees the
#use spi() statement.

If you do it the way you posted it, the compiler uses SPI1:
Quote:

.................... #USE SPI(SPI2, MODE=0, di=PIN_C4, do=PIN_C5, clk=PIN_C3, stream=SPI_TEST, BITS=8, BAUD=400000)
00032: MOVF SSP1BUF,W
00034: MOVFF param,SSP1BUF
00038: RRCF SSP1STAT,W
0003A: BNC 0038
0003C: MOVFF SSP1BUF,00
00040: GOTO 00A8 (RETURN)


But if you change the order of the lines so the #pin_select's come first,
Code:
#pin_select SDI2    = PIN_C4  // SPI2 Data Input      Pin 42
#pin_select SDO2    = PIN_C5  // SPI2 Data Output     Pin 43
#pin_select SCK2OUT = PIN_C3  // SPIC2 Clock Output   Pin 37

#USE SPI(SPI2, MODE=0, di=PIN_C4, do=PIN_C5, clk=PIN_C3, stream=SPI_TEST, BITS=8, BAUD=400000)

and re-compile, then it uses SPI2:
Quote:

.................... #USE SPI(SPI2, MODE=0, di=PIN_C4, do=PIN_C5, clk=PIN_C3, stream=SPI_TEST, BITS=8, BAUD=400000)
00032: MOVF SSP2BUF,W
00034: MOVFF paramSSP2BUF
00038: RRCF SSP2STAT,W
0003A: BNC 0038
0003C: MOVFF SSP2BUF,00
00040: GOTO 00A8 (RETURN)
....................


This was tested with CCS vs. 5.077.
Josep Robert



Joined: 27 Mar 2018
Posts: 25

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PostPosted: Thu Mar 29, 2018 1:56 am     Reply with quote

Summary

PIC18F47J13 SPI1
setup_spi (SPI_MASTER | SPI_L_TO_H | SPI_XMIT_L_TO_H);
spi_write(0x55);
It doesn't work!

PIC18F47J13 SPI1
#USE SPI(SPI1, MODE=0, STREAM=STREAM_SPI, BITS=8)
spi_xfer(STREAM_SPI, 0x55);
It doesn't work!

PIC18F47J13 SPI2
#pin_select SDI2 = PIN_C4 // SPI2 Data Input Pin 42
#pin_select SDO2 = PIN_C5 // SPI2 Data Output Pin 43
#pin_select SCK2OUT = PIN_C3 // SPIC2 Clock Output Pin 37

setup_spi2 (SPI_MASTER | SPI_L_TO_H | SPI_XMIT_L_TO_H);
spi_write2(0x55);
It works!

PIC18F47J13 SPI2
#pin_select SDI2 = PIN_C4 // SPI2 Data Input Pin 42
#pin_select SDO2 = PIN_C5 // SPI2 Data Output Pin 43
#pin_select SCK2OUT = PIN_C3 // SPIC2 Clock Output Pin 37

#USE SPI(SPI2, MODE=0, STREAM=SPI_TEST, BITS=8)
spi_xfer(SPI_TEST,0x55);
It works!


Finally we decided to change the problematic PIC18F47J13 with the better in all aspects PIC18F47K40.

Thanks for your patience with my first post in this forum. I've learnt a lot from you.

Josep Robert
Ttelmah



Joined: 11 Mar 2010
Posts: 19552

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PostPosted: Thu Mar 29, 2018 2:37 am     Reply with quote

It should have worked for SPI1 with the comma added. I cut out the stream name I was using, and typed in a new one, and managed to omit the comma, but that is working 'as is' except for this on my board. As I said though the key difference is I'm selecting a lower baud rate, and it was this I wanted you to test. I have a nasty suspicion that this chip is showing the same fault that a couple of others in the near family show, and won't work with a /1 division on SPI1. You added the comma, but also then had it selecting the maximum baud rate, which omitted what I wanted you to test... :(
Going to a better chip is definitely a good idea.
Josep Robert



Joined: 27 Mar 2018
Posts: 25

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PostPosted: Thu Mar 29, 2018 4:39 am     Reply with quote

With your original code:

Code:
#include <18F47J13.h>
#device ADC=10
#FUSES ADC10                                       // ADC is 10/12-bits
#FUSES NOWDT                                       // No Watch Dog Timer
#FUSES STVREN                                      // Stack full/underflow will cause reset
#FUSES NOXINST                                     // Extended set extension and Indexed Addressing mode disabled (Legacy mode)
#FUSES INTRC_IO                                    //Internal RC Osc, no CLKOUT
#FUSES NOCLOCKOUT           
#FUSES NOFCMEN                                     // Fail-safe clock monitor disabled
#FUSES NOIESO                                      // Internal External Switch Over mode disabled
#FUSES RTCOSC_INT                                  // RTCC uses Internal 31KHz Oscillator as reference source
#FUSES NODSBOR                                     // BOR disabled in Deep Sleep
#FUSES NODSWDT                                     // Deep Sleep Watchdog Timer disabled
#FUSES NOWPFP                                      // Write/Erase Protect Page
#FUSES SOSC_LOW                                    // Per defecte el CCS posa

#use delay(clock = 16MHZ, internal)

#USE SPI(SPI1, MODE=0, STREAM=SPI_TEST, BITS=8, BAUD=400000)

void main(void)
{
    delay_ms(100);
    while(TRUE)
    {
        spi_xfer(SPI_TEST,0x55);
    }
}


I obtain this:

https://imgur.com/a/gUdMS

It looks like random data on SDO pin.

Do not hesitate to ask me for any other test in my hardware if you need it.

Josep Robert
Ttelmah



Joined: 11 Mar 2010
Posts: 19552

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PostPosted: Thu Mar 29, 2018 6:27 am     Reply with quote

It is very strange.

Looking at the listing generated, it is writing 0x55 to the correct register, so ought to be working. The clock is being generated, so it is seeing a write as happening, but the data is not being output. I'ts more like it is clocking back out the 'old' contents of the buffer register clocked 'in' on the last transaction.
Now there is an issue with this chip, when operating in I2C mode, that it can't accept a write to the register for a few cycles after the flag sets to say that it can be written. I'm getting suspicious that the same issue is present in SPI mode. Now I'd have never noted it, since my code is doing a lot of other stuff between loading the buffer, so there is significant delay.
So something like:
Code:

void main(void)
{
    int8 dummy;
    delay_ms(100);
    while(TRUE)
    {
        dummy=spi_xfer(SPI_TEST,0x55);
        delay_cycles(4);
    }
}

Would be the 'bodge' to ensure that the write is not done too early in this case.
Josep Robert



Joined: 27 Mar 2018
Posts: 25

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PostPosted: Tue Apr 03, 2018 12:47 am     Reply with quote

With the modifications still doesn’t work. Sad

MPLAB X IDE v4.15
PCH Compiler CCS v5.076

Target device PIC18F47J13 found.
Device ID Revision = 0x1

Code:

#include <18F47J13.h>
#device ADC=10
#FUSES ADC10                                       // ADC is 10/12-bits
#FUSES NOWDT                                       // No Watch Dog Timer
#FUSES STVREN                                      // Stack full/underflow will cause reset
#FUSES NOXINST                                     // Extended set extension and Indexed Addressing mode disabled (Legacy mode)
#FUSES INTRC_IO                                    //Internal RC Osc, no CLKOUT
#FUSES NOCLOCKOUT           
#FUSES NOFCMEN                                     // Fail-safe clock monitor disabled
#FUSES NOIESO                                      // Internal External Switch Over mode disabled
#FUSES RTCOSC_INT                                  // RTCC uses Internal 31KHz Oscillator as reference source
#FUSES NODSBOR                                     // BOR disabled in Deep Sleep
#FUSES NODSWDT                                     // Deep Sleep Watchdog Timer disabled
#FUSES NOWPFP                                      // Write/Erase Protect Page
#FUSES SOSC_LOW                                    // Per defecte el CCS posa

#use delay(clock = 16MHZ, internal)

#USE SPI(SPI1, MODE=0, STREAM=SPI_TEST, BITS=8, BAUD=400000)

void main(void)
{
   int8 dummy;
    delay_ms(100);
    while(TRUE)
    {
        dummy=spi_xfer(SPI_TEST,0x55);
        delay_cycles(4);
    }
}

Pin 43 MOSI looks the same:
https://imgur.com/a/D1OuN
Ttelmah



Joined: 11 Mar 2010
Posts: 19552

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PostPosted: Tue Apr 03, 2018 12:59 am     Reply with quote

Start by talking to CCS. The basic example, and see what they say.
It may come down to needing to talk to MicroChip if there is a hardware problem with the chip, but CCS should be the first port of call here.
RF_Developer



Joined: 07 Feb 2011
Posts: 839

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PostPosted: Tue Apr 03, 2018 8:34 am     Reply with quote

Hmm, if I'm reading them right, all the 'scope readings show Voh of no more than 2.5V, which would barely be satisfactory at 3.3V Vcc, and totally unacceptable at 5V. If they are a indication of the true voltages, it would not surprise me at all that it didn't work or was "flakey", and works sometimes and not others for no obvious reason.

What is your circuit? What is your hardware set up? Where are these voltages measured?
Josep Robert



Joined: 27 Mar 2018
Posts: 25

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PostPosted: Tue Apr 03, 2018 11:05 am     Reply with quote

I've repeated the measurements with VDD=3.3V

https://imgur.com/a/tpuB6

Seems same result.

Thank you very much.

Best Regards,
Josep Robert
Ttelmah



Joined: 11 Mar 2010
Posts: 19552

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PostPosted: Tue Apr 03, 2018 11:20 am     Reply with quote

Does your Vcap/Vddcore capacitor meet the ESR requirements?. This needs to be a low ESR type (not a general electrolytic) and mounted close to the chip.
Ttelmah



Joined: 11 Mar 2010
Posts: 19552

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PostPosted: Tue Apr 03, 2018 1:21 pm     Reply with quote

I would add the following change to the code:
Code:

#include <18F47J13.h>
#device ADC=10
#FUSES ADC10                                       // ADC is 10/12-bits
#FUSES NOWDT                                       // No Watch Dog Timer
#FUSES STVREN                                      // Stack full/underflow will cause reset
#FUSES NOXINST                                     // Extended set extension and Indexed Addressing mode disabled (Legacy mode)
#FUSES INTRC_IO                                    //Internal RC Osc, no CLKOUT
#FUSES NOCLOCKOUT           
#FUSES NOFCMEN                                     // Fail-safe clock monitor disabled
#FUSES NOIESO                                      // Internal External Switch Over mode disabled
#FUSES RTCOSC_INT                                  // RTCC uses Internal 31KHz Oscillator as reference source
#FUSES NODSBOR                                     // BOR disabled in Deep Sleep
#FUSES NODSWDT                                     // Deep Sleep Watchdog Timer disabled
#FUSES NOWPFP                                      // Write/Erase Protect Page
#FUSES SOSC_LOW                                    // Per defecte el CCS posa

#use delay(clock = 16MHZ, internal)

#USE SPI(SPI1, MODE=0, STREAM=SPI_TEST, BITS=8, BAUD=400000)

void main(void)
{
    setup_adc_ports(NO_ANALOGS);
    delay_ms(100);
    while(TRUE)
    {
        spi_xfer(SPI_TEST,0x55);
    }
}

It appears that the default is to have all the ANSEL values set to analog. This causes odd behaviour when a peripheral is also setup on the same pins.
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