Read_bank and write_bank

[Flavio58]

Excuse me but I am a novice of PIC programming....

In my project I must to comunicate with a FPGA using PSP....
In CCS example I saw the read_bank and write_bank functions...
On CCS manual there is :

write_BANK(BANK, OFFSET, VALUE);

where bank may be 1-3 and offset 0-15 ....

Why 1-3 and offset 0-15 ?

On pic18f452 data sheet there is that the ram memory is divided into as many 16 banks that contains 256 bytes each.
It's not correct ?
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This message was ported from CCS's old forum
Original Post ID: 144515768

[R.J.Hamlett]

:=Excuse me but I am a novice of PIC programming....
:=
:=In my project I must to comunicate with a FPGA using PSP....
:=In CCS example I saw the read_bank and write_bank functions...
:=On CCS manual there is :
:=
:=write_BANK(BANK, OFFSET, VALUE);
:=
:=where bank may be 1-3 and offset 0-15 ....
:=
:=Why 1-3 and offset 0-15 ?
:=
:=On pic18f452 data sheet there is that the ram memory is divided into as many 16 banks that contains 256 bytes each.
:=It's not correct ?

The 'key' here, is that the read_bank, and write_bank functions, only really apply, as documented in the manual, with older devices, where it is possible to leave the main RAM pointer behaviour in '8bit' mode to save ROM useage. On these devices, the limits (at the time when the manual was written), apply. On the 18 devices, you can't work in this '8bit' mode, since all of the devices own registers are in higher banks, and there are special instructions for accessing some of these higher addresses. If you look at the 'availability' notes for the function, you will see, that it refers to PCB, and PCM compilers (and here allready says that it is of limited use), but makes no mention of the PCH compiler at all.
Basically the function has been overtaken by latter chips.

Best Wishes
___________________________
This message was ported from CCS's old forum
Original Post ID: 144515776