What will happen if adc channel exceed Vref?

[jani20]

What will happen if adc channel exceed Vref?
What value will the adc read return?
Thank you!

[rnielsen]

If your PIC is set to 10 bit resolution then the value will be 1023 (max value). If the input goes too far above VCC then the magic smoke could escape and the part will become a dead bug.

Ronald

[jani20]

Thank you!
The Vref will be divided from the Vcc:)

[kender]

[Ttelmah]

Some comments.
The 'Vref will be divided from Vcc'. Look at the data sheet. Note the figure for 'Iref'. Note that it changes when the ADC conversion is made (typically between 5uA to 150uA). Now if (for instance), you make Vref using (say) a 1K impedance 'divider' from Vcc, then this represents a potential change of voltage of up to 0.145v... Not good for accuracy. You need to consider a buffer amplifier on the Vref signal. The maximum recommended impedance of this source, varies with different chip models, but is typically 250R.
Now the maximum input 'range' on the analog pins, is the same as for any other normal pin (one diode drop below Vss, to one diode drop above Vdd). The 'range' for the full range of output numeric values (0 to 1023), is VrefL to VrefH, but there is no physical connection between the Vref pins, and the input pins, so provided the voltages don't go outside the legal input range, no 'magic smoke', need be involved!. However there is a caveat. You need to think carefully, if driving the signal(s) from reasonably low impedance sources, and they go outside the range of the supply rails, as to whether an external clamp should be used (if you rely on the internal clamp diodes, it can result in the supply rail being raised!...).
Beware also, to not get caught by the commonly made mistake here, of dividing by 1023, when converting to a 'value'. The divisor with the PIC ADC, is 1024 (it depends where the switching 'points' for the values are, whether the levels need to be treated like the 'fence posts', or like the panels between). The PIC ADC, switches to the top value, 1/1024th of the range below the Vref+ point, and doesn't switch from '0', till you are 1/1024th of the Vref range 'above' the 0v point (in 10 bit mode). Effectively Vref+, is already beyond the 'range' of the ADC (it would nominally mark the point at which the converter would switch to outputting 1024, if it could!). Have a look at AN546 (for one of the older PIC's), where figure1, shows the actual transfer function on the typical PIC ADC (in 8bit mode).
This is a large caveat, since many other ADC's in use, use the alternate transfer function, and should therefore use the 1023 divider. For accuracy, it is vital to check the data sheet, and know which type of ADC you are dealing with...

Best Wishes

[jani20]

Thank you for your detailed answer!
Can I make a unity gain buffer from a transistor?
Or I must use an OPA?

[Ttelmah]

The problem with a transistor, is the voltage drop. In emitter follower mode, the emitter will be basically 0.6v below the base, with this drop changing a little with load.
Look at AN546 which I mentioned. Consider just using a zener diode. For a simple application, this is the cheapest route to getting a pretty stable output with the change in load.

Best Wishes

[jani20]

And if I add some CAPs (exp:3x100nF) to the Vref pin after the voltage divider, can I get a low impedance source for the Vref pin?

The AN546 contains a table which shows the Vref sampling time
with various source impedance. But in the comment says: Assumes no external capacitors.

And the AN546 also says at the begin:
When using the external reference voltage, keep in mind that any analog input voltage must not exceed VREF.

So now what?

[Ttelmah]

You need to distinguish between the concepts, of what is 'safe', and what can be 'used'.
The maximum that can be _used_ by the ADC, is always Vref+ (to Vref-).
This is the range over which the output value has changes reflecting the changes in the input. However the chip can happily handle as a _safe_ input range, Vss-0.3 to Vdd+0.3. There is no direct connection between the inputs (so no current flow as a result of the input exceeding Vref) - just as applies between two analog inputs being at different voltages. However there _is_ a tendency to slightly elevate Vref. What happens, is that the internal capacitor used for sampling, gets charged to the higher input voltage, and then when the chip switches back to the Vref connection, this higher voltage is discharged through the internal reverse diode, into the Vref pin. The total current is limited by the internal resistances in the ADC (typically to a peak below 5mA worst case, and the total energy involved is tiny - the internal capacitance is very small), but this has the effect of elevating Vref, if this is not properly clamped.

Best Wishes